Datasheet

392
12.7.5 Contention between Buffer Register Write and Compare Match
If a compare-match occurs in the T
2
state of the TGR write cycle, data is transferred by the buffer
operation from the buffer register to the TGR. Data to be transferred differs depending on channels
0 and 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write (figures
12.79 and 12.80).
Buffer
register
Compare
match
signal
Compare
match buffer
signal
Address
Write signal
TGR
φ
T
1
T
2
TGR write cycle
Buffer register
address
NM
Buffer register write data
M
Figure 12.79 TGR Write and Compare-Match Contention (Channel 0)