Datasheet

390
12.7.3 Contention between TCNT Write and Clear
If a counter clear signal is issued in the T
2
state during the TCNT write cycle, TCNT clearing has
priority, and TCNT write is not conducted (figure 12.77).
Counter
clear signal
TCNT
Address
Write signal
φ
T
1
T
2
TCNT write cycle
TCNT address
N H'0000
Figure 12.77 TCNT Write and Clear Contention