Datasheet

388
Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed
by a 0 write. For DTC/DMA controller activation, clearing can also be done automatically. Figure
12.74 shows the timing for status flag clearing by the CPU. Figure 12.75 shows timing for clearing
due to the DTC/DMA controller.
Status flag
Interrupt
request signal
Address
Write signal
φ
T
1
T
2
TSR write cycle
TSR address
Figure 12.74 Timing of Status Flag Clearing by the CPU
Status flag
Interrupt
request signal
Address
φ
T
1
T
2
DTC/DMAC
read cycle
DTC/DMAC
write cycle
Source
address
Destination
address
T
1
T
2
Figure 12.75 Timing of Status Flag Clearing by DTC/DMAC Activation