Datasheet

365
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT3, 4 value
TGR4A
TDDR
TCNT3
TCNT4
Initial output
Time
Active level
TCNT3, 4 count start
(TSTR setting)

Complementary 
PWM mode
(TMDR setting)
Positive phase
output
Negative phase
output
Figure 12.44 Example of Initial Output in Complementary PWM Mode (2)