Datasheet

354
TGR3C
TDDR
TCNT3
TGR3D TGR4DTGR4C
TGR3B
Temp 1
TGR4A
Temp 2
TGR4B
Temp 3
TCNTS TCNT4
TGR3A TCDR
TCBR
Comparator
Comparator
Match
signal
Match
signal
Output controller
Output protection circuit
PWM cycle 
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
POE0
POE1
POE2
POE3
External cutoff

input
External cutoff 
interrupt
: Registers that can always be read or written from the CPU
: Registers that cannot be read or written from the CPU 
(except for TCNTS, which can only be read)

: Registers that can be read or written from the CPU
(but for which access disabling can be set by the bus controller)
TGR3A compare-

match interrupt TCNT4 underflow

interrupt
Figure 12.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode