Datasheet

353
Table 12.16 Register Settings for Complementary PWM Mode
Channel Counter/Register Description Read/Write from CPU
3 TCNT3 Start of up-count from value set
in dead time register
Maskable by BSC/BCR1
setting
*
TGR3A Set TCNT3 upper limit value
(1/2 carrier cycle + dead time)
Maskable by BSC/BCR1
setting
*
TGR3B PWM output 1 compare register Maskable by BSC/BCR1
setting
*
TGR3C TGR3A buffer register Always readable/writable
TGR3D PWM output 1/TGR3B buffer
register
Always readable/writable
4 TCNT4 Up-count start, initialized to
H'0000
Maskable by BSC/BCR1
setting
*
TGR4A PWM output 2 compare register Maskable by BSC/BCR1
setting
*
TGR4B PWM output 3 compare register Maskable by BSC/BCR1
setting
*
TGR4C PWM output 2/TGR4A buffer
register
Always readable/writable
TGR4D PWM output 3/TGR4B buffer
register
Always readable/writable
Timer dead time data register
(TDDR)
Set TCNT4 and TCNT3 offset
value (dead time value)
Maskable by BSC/BCR1
setting
*
Timer cycle data register
(TCDR)
Set TCNT4 upper limit value
(1/2 carrier cycle)
Maskable by BSC/BCR1
setting
*
Timer cycle buffer register
(TCBR)
TCDR buffer register Always readable/writable
Subcounter (TCNTS) Subcounter for dead time
generation
Read-only
Temporary register 1 (TEMP1) PWM output 1/TGR3B temporary
register
Not readable/writable
Temporary register 2 (TEMP2) PWM output 2/TGR4A temporary
register
Not readable/writable
Temporary register 3 (TEMP3) PWM output 3/TGR4B temporary
register
Not readable/writable
Note: * Access can be enabled or disabled according to the setting of bit 13 (MTURWE) in
BSC/BCR1 (bus controller/bus control register 1).