Datasheet

335
TGR0B
TGR0A
H'0000
TGR0C
TGR0A
TIOC0A
H'0450 H'0520
H'0200
H'0450
H'0520
H'0200
TCNT value
Time
Transfer
H'0450
H'0200
Figure 12.20 Buffer Operation Example (Output Compare Register)
Buffer Operation Examples—when TGR Is an Input Capture Register: Figure 12.21 shows
an example of TGRA set as an input capture register with the TGRA and TGRB registers set for
buffer operation.
The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture
input edge is selected as both rising and falling edge. Because buffer mode is selected, an input
capture A causes the TCNT counter value to be stored in the TGRA register, and the value that
was stored in the TGRA up until that time is simultaneously transferred to the TGRC register.
H'0F07
H'09FB
H'0532
H'0000
TGRA
TGRC
TIOCA
H'0532 H'09FBH'0F07
TCNT value
Time
H'0F07H'0532
Figure 12.21 Buffer Operation Example (Input Capture Register)