Datasheet

305

Channel 4 (TIOR4L Register):

• Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR4D register function.

Bit 7:

IOD3

Bit 6:

IOD2

Bit 5:

IOD1

Bit 4:

IOD0 Description

0 0 0 0 TGR4D Output disabled (initial value)

1 is an Initial Output 0 on compare-match

1 0 output output Output 1 on compare-match

1 compare is 0 Toggle output on compare-match

1 0 0 register Output disabled

1 Initial Output 0 on compare-match

1 0 output Output 1 on compare-match

1 is 1 Toggle output on compare-match

1 0 0 0 TGR4D Capture Input capture on rising edge

1 is an input source Input capture on falling edge

1 0 input is the Input capture on both edges

1 capture TIOC4D pin

1 0 0 register Input capture on rising edge

1 Input capture on falling edge

1 0 Input capture on both edges

Note: When the BFB bit of TMDR4 is set to 1 and TGR4D is being used as a buffer register, these

settings become ineffective and input capture/output compares do not occur.