Datasheet

289
• Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal
operation, or buffer operation in combination with the TGRC register. When using TGRC as a
buffer register, no TGRC register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0,
and cannot be modified.
Bit 4: BFA Description
0 TGRA operates normally (initial value)
1 TGRA and TGRC buffer operation
• Bits 3–0—Modes 3–0 (MD3–MD0): These bits set the timer operation mode.
Bit 3:
MD3
Bit 2:
MD2
Bit 1:
MD1
Bit 0:
MD0 Description
0000 Normal operation (initial value)
1 Reserved (do not set)
1 0 PWM mode 1
1 PWM mode 2
*
1
1 0 0 Phase counting mode 1
*
2
1 Phase counting mode 2
*
2
1 0 Phase counting mode 3
*
2
1 Phase counting mode 4
*
2
1000 Reset synchronous PWM mode
*
3
1 Reserved (do not set)
1 0 Reserved (do not set)
1 Reserved (do not set)
1 0 0 Reserved (do not set)
1 Complementary PWM mode 1 (transmit at peak)
*
3
1 0 Complementary PWM mode 2 (transmit at valley)
*
3
1 Complementary PWM mode 3 (transmit at peak and valley)
*
3
Notes: *1 PWM mode 2 can not be set for channels 3, 4.
*2 Phase measurement mode can not be set for channels 0, 3, 4.
*3 Reset synchronous PWM mode, complementary PWM mode can only be set for
channel 3. When channel 3 is set to reset synchronous PWM mode or complementary
PWM mode, the channel 4 settings become ineffective and automatically conform to the
channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or
complementary PWM mode. Reset synchronous PWM mode and complementary PWM
mode can not be set for channels 0, 1, 2.