Datasheet

281
Table 12.3 Register Configuration (cont)
Chan-
nel Name
Abbrevi-
ation R/W
Initial
Value Address
Access Size
(Bits)
*
1
2 Timer control register 2 TCR2 R/W H'00 H'FFFF82A0 8, 16, 32
Timer mode register 2 TMDR2 R/W H'C0 H'FFFF82A1
Timer I/O control register 2 TIOR2 R/W H'00 H'FFFF82A2
Timer interrupt enable
register 2
TIER2 R/W H'40 H'FFFF82A4
Timer status register 2 TSR2 R/(W)
*
2
H'C0 H'FFFF82A5
Timer counter 2 TCNT2 R/W H'0000 H'FFFF82A6 16, 32
General register 2A TGR2A R/W H'FFFF H'FFFF82A8
General register 2B TGR2B R/W H'FFFF H'FFFF82AA
3 Timer control register 3 TCR3 R/W
*
3
H'00 H'FFFF8200 8, 16, 32
Timer mode register 3 TMDR3 R/W
*
3
H'C0 H'FFFF8202
Timer I/O control register 3H TIOR3H R/W
*
3
H'00 H'FFFF8204
Timer I/O control register 3L TIOR3L R/W
*
3
H'00 H'FFFF8205
Timer interrupt enable
register 3
TIER3 R/W
*
3
H'40 H'FFFF8208
Timer status register 3 TSR3 R/(W)
*
2
H'C0 H'FFFF822C 8, 16, 32
Timer counter 3 TCNT3 R/W
*
3
H'0000 H'FFFF8210 16, 32
General register 3A TGR3A R/W
*
3
H'FFFF H'FFFF8218
General register 3B TGR3B R/W
*
3
H'FFFF H'FFFF821A
General register 3C TGR3C R/W H'FFFF H'FFFF8224 16, 32
General register 3D TGR3D R/W H'FFFF H'FFFF8226
4 Timer control register 4 TCR4 R/W
*
3
H'00 H'FFFF8201 8, 16, 32
Timer mode register 4 TMDR4 R/W
*
3
H'C0 H'FFFF8203
Timer I/O control register 4H TIOR4H R/W
*
3
H'00 H'FFFF8206
Timer I/O control register 4L TIOR4L R/W
*
3
H'00 H'FFFF8207
Timer interrupt enable
register 4
TIER4 R/W
*
3
H'40 H'FFFF8209
Timer status register 4 TSR4 R/(W)
*
2
H'C0 H'FFFF822D 8, 16, 32