Datasheet

280
12.1.4 Register Configuration
Table 12.3 summarizes the MTU register configuration.
Table 12.3 Register Configuration
Chan-
nel Name
Abbrevi-
ation R/W
Initial
Value Address
Access Size
(Bits)
*
1
Shared Timer start register TSTR R/W H'00 H'FFFF8240 8, 16, 32
Timer synchro register TSYR R/W H'00 H'FFFF8241
0 Timer control register 0 TCR0 R/W H'00 H'FFFF8260
Timer mode register 0 TMDR0 R/W H'C0 H'FFFF8261
Timer I/O control register 0H TIOR0H R/W H'00 H'FFFF8262
Timer I/O control register 0L TIOR0L R/W H'00 H'FFFF8263
Timer interrupt enable
register 0
TIER0 R/W H'40 H'FFFF8264
Timer status register 0 TSR0 R/(W)
*
2
H'C0 H'FFFF8265
Timer counter 0 TCNT0 R/W H'0000 H'FFFF8266 16, 32
General register 0A TGR0A R/W H'FFFF H'FFFF8268
General register 0B TGR0B R/W H'FFFF H'FFFF826A
General register 0C TGR0C R/W H'FFFF H'FFFF826C
General register 0D TGR0D R/W H'FFFF H'FFFF826E
1 Timer control register 1 TCR1 R/W H'00 H'FFFF8280 8, 16, 32
Timer mode register 1 TMDR1 R/W H'C0 H'FFFF8281
Timer I/O control register 1 TIOR1 R/W H'00 H'FFFF8282
Timer interrupt enable
register 1
TIER1 R/W H'40 H'FFFF8284
Timer status register 1 TSR1 R/(W)
*
2
H'C0 H'FFFF8285
Timer counter 1 TCNT1 R/W H'0000 H'FFFF8286 16, 32
General register 1A TGR1A R/W H'FFFF H'FFFF8288
General register 1B TGR1B R/W H'FFFF H'FFFF828A