Datasheet

277
TCR
Channel 0 Channel 1 Channel 2 Channel 4 Channel 3Shared
Control logic
Channels 0–2 control logic Channels 3, 4 control logic
TMDR
TIORH TIORL
TIER TSR
TCR TMDR
TIOR
TIER TSR
TCR TMDR
TIOR
TIER TSR TSTR TSYR
TCR TMDR
TIOR TIORL
TIER TSR
TCR TMDR
TIORH TIORL
TIER TSR
TOER TOCR
TGCR
TCNT
BUS I/F
TGRA
TGRD
TGRB
TGRC
TCNTS
TDDR TCDR
TCBR
TCNT
TGRA
TGRD
TGRB
TGRC
TCNT
TGRA TGRB
TCNT
TGRA TGRB
TCNT
TGRA
TGRD
TGRB
TGRC
(I/O pins)
Channel 3:
TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4:
TIOC4A
TIOC4B
TIOC4C
TIOC4D
(Clock input)
Internal clock: 
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
(I/O pins)
Channel 0:
TIOC0A
TIOC0B
TIOC0C
TIOC0D
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
Channel 1:
TIOC1A
TIOC1B
Channel 2:
TIOC2A
TIOC2B
Internal data bus
A/D conversion
start request signal
(Interrupt
request signals)
Channel 3:
TGI3A
TGI3B
TGI3C
TGI3D
TGI3V
Channel 4:
TGI4A
TGI4B
TGI4C
TGI4D
TGI4V
(Interrupt
request signal)
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TGI0V
Channel 1:
TGI1A
TGI1B
TGI1V
TGI1U
Channel 2:
TGI2A
TGI2B
TGI2V
TGI2U
Module data bus

Figure 12.1 MTU Block Diagram