Datasheet

260
CK
DREQ
DRAK
Bus
cycle
DACK
CPU CPUCPU
DMAC(R)
DMAC(R) DMAC(R)
DMAC(R)DMAC(W)
DMAC(W)
DMAC(W)
DMAC(W)
Figure 11.23 Burst Mode, Dual Address, and Edge Detection