249
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU CPU
DMAC(R)
DMAC
(R)
DMAC(W)
1st sampling 2nd sampling
Note: With cycle-steal and dual address operation, sampling timing is the same
whether DREQ detection is by level or by edge.
Figure 11.16 Cycle Steal, Dual Address, and Level Detection (Normal Operation)
