Datasheet

248
CK
D
REQ
DRAK
Bus
cycle
DACK
CPU(3) CPU(4) CPU(5) CPU(2)CPU(1)
1st sampling 2nd sampling
DMAC(R)
DMAC(R)DMAC(W)
DMAC(W)
DMAC(W)DMAC(R)
Figure 11.15 Cycle Steal, Dual Address, and Level Detection (Fastest Operation)