Datasheet

239
Data read cycle

Data write cycle

Transfer destination
address
Transfer source 
address
CK

(1st cycle)
(2nd cycle)
A21–A0
CSn
D15–D0
RD
WRH, WRL
DACK
Note: Transfer between external memories with DACK are output during read
cycle.
Figure 11.8 Example of Direct Address Transfer Timing in Dual Address Mode