Datasheet

221
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the
operation and transmission of each channel is designated. They are initialized by a power-on reset
and in software standby mode. There is no initializing with manual reset.
Bit: 31 30 29 28 27 26 25 24
————————
Initial value: — — — — — — — —
R/W: R R R R R R R R
Bit: 23 22 21 20 19 18 17 16
———DI
*
2
RO
*
2
RL
*
2
AM
*
2
AL
*
2
Initial value: — — — 0 0 0 0 0
R R R (R/W) (R/W) (R/W) (R/W) (R/W)
Bit: 15 14 13 12 11 10 9 8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
—DS
*
2
TM TS1 TS0 IE TE DE
Initial value: — 0 0 0 0 0 0 0
R/W: R (R/W) R/W R/W R/W R/W R/(W)
*
1
R/W
Notes: *1 TE bit: Allows only 0 write after reading 1.
*2 The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
• Bits 31–21—Reserved bits: Data are 0 when read. The write value always be 0.
• Bit 20—Direct/Indirect (DI): Specifies either direct address mode operation or indirect address
mode operation for channel 3 source address. This bit is valid only in CHCR3. It always reads
0 for CHCR0–CHCR2, and cannot be modified.
Bit 20: DI Description
0 Direct access mode operation for channel 3 (initial value)
1 Indirect access mode operation for channel 3