Datasheet

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11.1.2 Block Diagram
Figure 11.1 is a block diagram of the DMAC.
On-chip ROM
Peripheral bus
Internal bus
On-chip RAM
DREQ0, DREQ1
Circuit
control
SARn
DMAC module
Register
control
Activation
control
Request
priority
control
Bus interface
Bus state
controller
On-chip
peripheral
module
DARn
DMATCRn
CHCRn
DMAOR
MTU
SCI0, SCI1
A/D converter
*
DEIn
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
DACK0, DACK1
DRAK0, DRAK1
SARn:
DARn:
DMATCRn:
CHCRn:
DMAOR:
n:
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
DMAC operation register
0, 1, 2, 3
Note: * A/D1 for A mask and A/D for others
Figure 11.1 DMAC Block Diagram