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Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 144 (20x20) 32-Bit 28.7 MHz I/O number 98
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Channel 3: Dual address mode only. Direct address transfer mode and indirect address
transfer mode selectable.
• Reload function: Enables automatic reloading of the value set in the first source address
register every fourth DMA transfer. This function can be executed on channel 2 only.
• Transfer requests: There are three DMAC transfer activation requests, as indicated below.
External request: From two DREQ pins. DREQ can be detected either by falling edge or by
low level. External requests can only be received on channels 0 or 1.
Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as
SCI or A/D. These can be received by all channels.
Auto-request: The transfer request is generated automatically within the DMAC.
• Selectable bus modes: Cycle-steal mode or burst mode
• Two types of DMAC channel priority ranking:
Fixed priority mode: Always fixed
Round robin mode: Sets the lowest priority level for the channel that received the execution
request last
• CPU can be interrupted when the specified number of data transfers are complete.