208
SH704x
CSCSn
RD OE
A0
A1
A2–A18 A0–A16
WRHH WE
D24–D31 I/O0–I/O7
WRHL
D16–D23
D0–D7
WRL
WRH
D8–D15
CS
OE
A0–A16
WE
I/O0–I/O7
CS
OE
A0–A16
WE
I/O0–I/O7
I/O0–I/O7
CS
OE
A0–A16
WE
128k × 8 bits
SRAM
Figure 10.28 32-Bit Data Bus Width SRAM Connection
