Datasheet

194
T
p
T
c1
T
cw1
T
cw2
T
cw0
T
c2
T
r
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row Column
WAIT
Figure 10.11 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD= 0, Two Waits + Wait Due
to WAIT Signal)