Datasheet

193
T
p
T
c1
T
cw1
T
cw2
T
cw3
T
c2
T
r
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row Column
Figure 10.10 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, Three Waits)