Datasheet

192
T
p
T
r
T
rw
T
c1
T
cw1
T
cw2
T
cw2
T
pw
CK
Write
Read
Address
Data
RAS
CASx
RDWR
Data
RDWR
CASx
RAS
Row Column
Figure 10.9 DRAM Bus Cycle (Normal Mode, TPC = 1, RCD = 1, Two Waits)