Datasheet

Section Page Description
Appendix C Pin
States
Table C.2 Pin
Modes During Reset,
Power-Down, and
Bus Right Release
Modes (112 Pin,
120 Pin) (cont)
868
Table amended
Pin modes
Pin Function Reset Power-Down
Bus Right Standby in Bus
Class Pin Name Power-On Manual Standby Sleep Release Right Release
Port
control
POE0–POE3 Z
*
4
IZII Z
SCI SCK0–SCK1 Z
*
4
I/O Z I/O I/O Z
TXD0–TCD1 Z
*
4
OO
*
1
OO O
*
1
RXD0–RXD1 Z
*
4
IZII Z
A/D
converter
ADTRG Z
*
4
IZII Z
control
AN0–AN7 Z I Z I I Z
I/O Port PA0–PA15 Z
*
4
I/O K
*
1
K I/O K
*
1
PB0–PB9
PC0–PC15
PD0–PD15
PE0–PE8–PE10
PE9,PE11–PE15 Z
*
4
I/O Z K I/O Z
PF0–PF7 Z I Z I I Z
Notes: 1. There are instances where bus right release and transition to software standby mode
occur simultaneously due to the timing between BREQ and internal operations. In such
cases, standby mode results, but the standby state may be different.
The initial pin states depend on the mode. See section 18, Pin Function Controller
(PFC), for details.
2. I: Input, O: Output, H: High-level output, L: Low-level output, Z: High impedance,
K: Input pin with high impedance, output pin mode maintained.
*1 If the standby control register port high-impedance bits are set to 1, output pins become
high impedance.
*2A21–A18 will become input ports after power-on reset.
*3 Input in the SH7044/SH7045 F-ZTAT version.
*4 General use I/O ports PAn, PBn, PCn, PDn, and PEn, as well as pins multiplexed with
them, are unstable during the RES setup time (t
RESS
) immediately after the RES pin
goes to low level.