Datasheet

188
10.3.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period
beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 10.6. T
h
and T
f
cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these
cycles; RD and WRx signals are not. Further, data is extended up to the T
f
cycle, which is
effective for gate arrays and the like, which have slower write operations.
T
h
T
1
CK
Read
Write
Address
CSn
RD
Data
WRx
Data
T
2
T
f
DACK
Figure 10.6 CS Assert Period Extension Function