Datasheet

187
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 10.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when T
w
state shifts to T
2
state.
T
1
T
W
CK
Read
Write
Address
CSn
WAIT
RD
Data
WRx
Data
T
W
T
W0
T
2
Figure 10.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait
2 State + WAIT Signal)