Datasheet

181
• Bits 3–2—DRAM Bus Width Specification (SZ1, SZ0): Specifies the DRAM space bus width.
Bit 3 (SZ1) Bit 2 (SZ0) Description
0 0 Byte (8 bits) (initial value)
1 Word (16 bits)
1 Don’t care Longword (32 bits)
• Bits 1–0—DRAM Address Multiplex (AMX1–AMX0): Specifies the DRAM address
multiplex count.
Bit 1 (AMX1) Bit 0 (AMX0) Description
0 0 9 bit (initial value)
1 10 bit
1 0 11 bit
1 12 bit
10.2.6 Refresh Timer Control/Status Register (RTCSR)
RTCSR is a 16-bit read/write register that selects the refresh mode and the clock input to the
refresh timer counter (RTCNT), and controls compare match interrupts (CMI).
RTCSR is initialized by power-on resets and hardware standbys to H'0000, but is not initialized by
manual resets or software standbys.
Bit: 15 14 13 12 11 10 9 8
————————
Initial value: 0 0 0 0 0 0 0 0
R/W: R R R R R R R R
Bit: 7 6 5 4 3 2 1 0
— CMF CMIE CKS2 CKS1 CKS0 RFSH RMD
Initial value: 0 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R/W R/W R/W R/W
• Bits 15–7—Reserved: These bits always read as 0. The write value should always be 0.