Datasheet

179
Bit: 15 14 13 12 11 10 9 8
TPC RCD TRAS1 TRAS0 DWW1 DWW0 DWR1 DWR0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
DIW — BE RASD SZ1 SZ0 AMX1 AMX0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R R/W R/W R/W R/W R/W R/W
• Bit 15—RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after
RAS is negated before next assert.
Bit 15 (TPC) Description
0 1.5 cycles (initial value)
1 2.5 cycles
• Bit 14—RAS-CAS Delay Cycle Count (RCD): Specifies the number of row address output
cycles.
Bit 14 (RCD) Description
0 1 cycle (initial value)
1 2 cycles
• Bits 13–12—CAS-Before-RAS Refresh RAS Assert Cycle Count (TRAS1–TRAS0): Specify
the number of RAS assert cycles for CAS before RAS refreshes.
Bit 13 (TRAS1) Bit 12 (TRAS0) Description
0 0 2.5 cycles (initial value)
1 3.5 cycles
1 0 4.5 cycles
1 5.5 cycles