Datasheet

174
Bit 9 (IW01) Bit 8 (IW00) Description
0 0 No idle cycle after accessing CS0 space
1 Inserts one idle cycle
1 0 Inserts two idle cycles
1 Inserts three idle cycles (initial value)
• Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by
once negating the CSn signal when doing consecutive accesses of the same CS space. When a
write immediately follows a read, the number of idle cycles inserted is the larger of the two
values specified by IW and CW. Refer to section 10.6, Waits between Access Cycles, for
details.
CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access
idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0
specifies the continuous access idles for CS0 space.
Bit 7 (CW3) Description
0 No CS3 space continuous access idle cycles
1 One CS3 space continuous access idle cycle (initial value)
Bit 6 (CW2) Description
0 No CS2 space continuous access idle cycles
1 One CS2 space continuous access idle cycle (initial value)
Bit 5 (CW1) Description
0 No CS1 space continuous access idle cycles
1 One CS1 space continuous access idle cycle (initial value)
Bit 4 (CW0) Description
0 No CS0 space continuous access idle cycles
1 One CS0 space continuous access idle cycle (initial value)