Datasheet

172
• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size when A1LG =
0.
Bit 1 (A1SZ) Description
0 Byte (8 bit) size
1 Word (16 bit) size (initial value)
Note: This bit is ignored when A1LG = 1; CS1 space bus size becomes longword (32 bit).
• Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size when A0LG =
0.
Bit 0 (A0SZ) Description
0 Byte (8 bit) size
1 Word (16 bit) size (initial value)
Note: A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode,
the CS0 space bus size is specified by the mode pin. However, even in on-chip ROM
effective mode, this bit is ignored when A0LG = 1; CS0 space bus size becomes longword
(32 bit).
10.2.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert
extension of each CS space.
BCR2 is initialized by power-on resets to H'FFFF, but is not initialized by manual resets or
software standbys.
Bit: 15 14 13 12 11 10 9 8
IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0
Initial value: 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W