Datasheet

165
10.1.3 Pin Configuration
Table 10.1 shows the bus state controller pin configuration.
Table 10.1 Pin Configuration
Signal I/O Description
A21–A0 O Address output (A21–A18 will become input ports with power-on reset)
D31–D0 I/O 32-bit data bus. D15-D0 are address output and data I/O during address/data
multiplex I/O.
CS0–
CS3
O Chip select
RD O Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also
output during DRAM access.
WRHH O Strobe that indicates a write cycle to the most significant byte (D31–D24) for
ordinary space/multiplex I/O. Also output during DRAM access.
WRHL O Strobe that indicates a write cycle to the 2nd byte (D23–D16) for ordinary
space/multiplex I/O. Also output during DRAM access.
WRH O Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
WRL O Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
RDWR O Strobe indicating a write cycle to DRAM (used for DRAM space)
RAS O RAS signal for DRAM (used for DRAM space)
CASHH O CAS signal when accessing the most significant byte (D31–D24) of DRAM
(used for DRAM space)
CASHL O CAS signal when accessing the 2nd byte (D23–D16) of DRAM (used for DRAM
space)
CASH O CAS signal when accessing the 3rd byte (D15–D8) of DRAM (used for DRAM
space)
CASL O CAS signal when accessing the least significant byte (D7–D0) of DRAM (used
for DRAM space)
AH O Signal to hold the address during address/data multiplex
WAIT I Wait state request signal
BREQ I Bus release request input
BACK O Bus use enable output