Datasheet
164
10.1.2 Block Diagram
Figure 10.1 shows the BSC block diagram.
WCR1
WCR2
BCR1
BCR2
DCR
RD
CMI interrupt request
WAIT
RTCSR
RTCNT
RTCOR
Internal bus
Interrupt
controller
Bus
interface
Area
control
unit
Comparator
Module bus
CS0 to CS3
AH
RDWR
Wait
control
unit
Memory
control
unit
Peripheral bus
WRHH, WRHL
WRH, WRL
CASHH, CASHL
CASH, CASL
RAS
BSC
WCR1:
WCR2:
BCR1:
BCR2:
Wait control register 1
Wait control register 2
Bus control register 1
Bus control register 2
DCR:
RTCNT:
RTCOR:
RTSCR:
DRAM area control register
Refresh timer counter
Refresh timer constant register
Refresh timer control/status register
Figure 10.1 BSC Block Diagram