Datasheet

162
Idle cycle
Idle cycle
Idle cycle
CK
Internal
address
Address
RAS
CASxx
Data
ROW COLUMN
Miss-hit
RAS assert extension
Figure 9.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space
(Normal Mode, TPC = 0, RCD = 0, No Wait)
Miss-hit
ROW COLUMN CS space
Wait
COLUMN
RAS assert extension
CK
Internal
address
Address
RAS
CASxx
Data
DRAM access
CS space
access
DRAM access
Miss-hit
Figure 9.8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space
(RAS Down Mode, TPC = 0, RCD = 0, No Wait)
9.4.4 Cache Hit after Cache Miss
The first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle
cycle generation is performed. The next hit operates as a cache hit.