Datasheet

158
• Bit 3—CS3 Space Cache Enable (CECS3): Selects whether to use CS3 space as a cache object
(enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 3 (CECS3) Description
0 CS3 space cache disabled (initial value)
1 CS3 space cache enabled
• Bit 2—CS2 Space Cache Enable (CECS2): Selects whether to use CS2 space as a cache object
(enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 2 (CECS2) Description
0 CS2 space cache disabled (initial value)
1 CS2 space cache enabled
• Bit 1—CS1 Space Cache Enable (CECS1): Selects whether to use CS1 space as a cache object
(enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 1 (CECS1) Description
0 CS1 space cache disabled (initial value)
1 CS1 space cache enabled
• Bit 0—CS0 Space Cache Enable (CECS0): Selects whether to use CS0 space as a cache object
(enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 0 (CECS0) Description
0 CS0 space cache disabled (initial value)
1 CS0 space cache enabled
9.3 Address Array and Data Array
There is a special cache space for controlling the cache. This space is divided into an address array
and a data array, where addresses (tag address, including valid bit) and data (4-byte line length) for
cache control are recorded. The special cache space is shown in table 9.2. It can be used as on-chip
RAM space when the cache is not being used.