Datasheet

157
Table 9.1 Register Configuration
Name Abbreviation R/W
Initial
Value Address
Access Size
(Bits)
Cache control register CCR R/W H'0000
*
H'FFFF8740 8, 16, 32
Note: * Bits 15–5 are undefined.
9.2 Register Explanation
9.2.1 Cache Control Register (CCR)
The cache control register (CCR) selects the cache enable/disable of each space.
The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is
not initialized by manual resets or standby mode.
Bit: 15 14 13 12 11 10 9 8
————————
Initial value: ********
R/W: R R R R R R R R
Bit: 7 6 5 4 3 2 1 0
———CE
DRAM
CE
CS3
CE
CS2
CE
CS1
CE
CS0
Initial value: ***00000
R/W: R R R R/W R/W R/W R/W R/W
Note: * Bits 15–5 are undefined.
• Bits 15–5—Reserved: Reading these bits gives undefined values. The write value should
always be 0.
• Bit 4—DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a
cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 4 (CEDRAM) Description
0 DRAM space cache disabled (initial value)
1 DRAM space cache enabled