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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 144 (20x20) 32-Bit 28.7 MHz I/O number 98
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9.1.2 Block Diagram
Figure 9.2 shows a block diagram of the cache.
CCR: Cache control register
Cache tag
Cache
controller
Cache data
Internal address bus
Internal data bus
Bus state
controller
External bus
interface
CCR
Cache
Figure 9.2 Cache Block Diagram
9.1.3 Register Configuration
The cache has one register, which can be used to control the enabling or disabling of each cache
space. The register configuration is shown in table 9.1.