Datasheet

152
Table 8.6 Execution State of DTC
Mode Vector Read I
Register
Information
Read/Write J Data Read K Data Write L
Internal
Operation M
Normal 1 7 1 1 1
Repeat 1 7 1 1 1
Block transfer 1 7 N N 1
Note: N: block size (default set values of DTCRB)
Table 8.7 State Counts Needed for Execution State
Access Objective
On-
chip
RAM
On-
chip
ROM
Internal I/O
Register External Device
Bus width 32 32 32 8 16 32
Access
state
112
*
1
3
*
2
222
Execution Vector read S
I
—1 — 4 2 2
state
Register information
read/write
S
J
11— 842
Byte data read S
K
1123222
Word data read S
K
1123422
Long word data read S
K
1146842
Byte data write S
L
1123222
Word data write S
L
1123422
Long word write S
L
1146842
Internal operation S
M
1
Notes: *1 Two state access module : port, INT, CMT, SCI, etc.
*2 Three state access module : WDT, CACHE, UBC, etc.
The execution state count is calculated using the following formula. ∑ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is 1).
Execution state count = I · S
I
+ ∑ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M