Datasheet

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25.4 A/D Converter
Characteristics
Table 25.16 A/D
Converter Timing (A
mask)
779
Table amended
Non-linearity error
Offset error
*
*
Full scale error
*
Quantize error
*
26.2 DC
Characteristics
Table 26.2 DC
Characteristics
782
Table amended
Schmitt
trigger input
voltage
PA2, PA5, PA6–
PA9,
PE0–PE15
V
T
+
– V
T
–
V
CC
×
0.07
——
V
VT
+
≥ V
CC
× 0.9V (min)
VT
–
≤ V
CC
× 0.2V (max)
783
Table amended
Analog
supply
AI
CC
— 48
mA f = 16.7MHz
current
AI
ref
— 0.5 1
*
3
mA QFP144 version only
*3 2 mA in the A mask version of MASK products.
26.3.2 Control
Signal Timing
Table 26.5 Control
Signal Timing
786
Note amended
Notes: *1 SH7042/43 ZTAT (excluding A mask) are 3.2V.
*2 The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals
are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to
have produced changes at clock rise (for RES, MRES,
BREQ) or clock fall (for NMI and IRQ7–IRQ0). If the
setup times are not provided, recognition is delayed until
the next clock rise or fall.
26.3.3 Bus Timing
Figure 26.12 DRAM
Cycle (Normal Mode,
1 Wait, TPC = 0,
RCD = 0)
795
Figure amended
Tcw1 Tc2
t
CASD1
t
CAC
t
RAC
t
AA
t
RDS
Column address