Datasheet

138
• Bit 5—DTC Interrupt Select (DISEL): This bit designates whether to prohibit or allow
interrupt requests to the CPU after one-time DTC transfers.
Bit 5 (DISEL) Description
0 Prohibit interrupts to the CPU after DTC data transfer completion if the
transfer counter is not 0 (DTC clears the interrupt source flag of the
activating source to 0)
1 Allow interrupts to the CPU after DTC data transfer completion (DTC
clears the DTER bit for the interrupt of the activating source to 0)
• Bit 4—DTC NMI Mode (NMIM): This bit designates whether to terminate transfers when an
NMI is input during DTC transfers.
Bit 4 (NMIM) Description
0 Terminate DTC transfer upon an NMI
1 Continue DTC transfer until end of transfer being executed
• Bits 3–0—Reserved: They have no effect on DTC operation.
8.2.2 DTC Source Address Register (DTSAR)
The DTC source address register (DTSAR) is a 32-bit register that specifies the DTC transfer
source address. An even address indicates that the transfer size is word; a multiple-of-four address
means it is longword. The contents of this register is located in memory.
Bit: 31 30 29 28 27 … 43210
…
Initial value: *****… *****
R/W: — — — — — … — — — — —
Note: * Initial value is undefined.
8.2.3 DTC Destination Address Register (DTDAR)
The DTC destination address register (DTDAR) is a 32-bit register that specifies the DTC transfer
destination address. An even address indicates that the transfer size is word; a multiple-of-four
address means it is longword. The contents of this register are located in memory.