Datasheet

134
8.1.2 Block Diagram
Figure 8.1 shows the DTC block diagram. DTC transfer information is located in memory.
CPU interrupt request
source clear control
Interrupt request
DTC
On-chip
ROM
On-chip
RAM
On-chip
peripheral
module
Peripheral bus
External bus
External
memory
Bus controller
Register
control
Activation
control
Request
priority
control
Bus interface
DTC module bus
DTMR
DTCR
DTSAR
DTDAR
DTIAR
DTER
DTCSR
DTBR
Internal bus
DTMR:
DTCR:
DTSAR:
DTDAR:

DTC mode register
DTC count register
DTC source address register
DTC destination address register

DTIAR:
DTER:
DTCSR:
DTBR:
DTC initial address register
DTC enable register
DTC control/status register
DTC information base register

External
device
(memory-
mapped)
Figure 8.1 DTC Block Diagram