Datasheet

Section Page Description
25.3.3 Bus Timing
Figure 25.14 DRAM
Cycle (Normal Mode,
3 Waits, TPC=1,
RCD=1)
764 Figure amended
Tcw1 Tcw2
t
CASD1
t
CAC
t
AA
Column
25.3.5 Multifunction
Timer Pulse Unit
Timing
Figure 25.23 MTU
I/O Timing
770 Figure amended
t
TOCD
Figure 25.24 MTU
Clock Input Timing
770 Figure amended
t
TCKS
25.3.11 Measuring
Conditions for AC
Characteristics
Figure 25.33 Output
Load Circuit
778
Title amended
Output Load Circuit