
127
SZ1 SZ0
User
break
interrupt
RW1 RW0
ID1 ID0
CP1 CP0
UBARH/UBARL UBAMRH/UBAMRL
32
32
32
32
32
Internal address
bits 31–0
CPU cycle
DMA/DTC cycle
Instruction fetch
Data access
Read cycle
Write cycle
Byte size
Word size
Longword size
Figure 7.2 Break Condition Judgment Method