Datasheet

122
UBARL:
Bit: 15 14 13 12 11 10 9 8
UBARL UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
UBARL UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• UBARH Bits 15–0—User Break Address 31–16 (UBA31–UBA16): These bits store the upper
bit values (bits 31–16) of the address of the break condition.
• UBARL Bits 15–0—User Break Address 15–0 (UBA15–UBA0): These bits store the lower bit
values (bits 15–0) of the address of the break condition.
7.2.2 User Break Address Mask Register (UBAMR)
The user break address mask register (UBAMR) consists of user break address mask register H
(UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH designates whether to mask any of the break address bits
established in the UBARH, and UBAMRL designates whether to mask any of the break address
bits established in the UBARL. Resets and hardware standbys initialize both UBAMRH and
UBAMRL to H'0000. They are not initialized in manual reset or software standby mode.
UBAMRH:
Bit: 15 14 13 12 11 10 9 8
UBAMRH UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
UBAMRH UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W