Datasheet

Section Page Description
25.2 DC
Characteristics
Table 25.2 DC
Characteristics
751 Note amended
*2 5 mA in the A mask version, except for F-ZTAT products.
25.3.2 Control
Signal Timing
Table 25.5 Control
Signal Timing
754 Note amended
Note: * The RES, MRES, NMI, BREQ, and IRQ7IRQ0 signals are
asynchronous inputs, but when thesetup times shown here
are provided, the signals are considered to have produced
changes at clock rise (for RES, MRES, BREQ) or clock fall
(for NMI and IRQ7IRQ0). If the setup times are not
provided, recognition is delayed until the next clock rise or
fall.
25.3.3 Bus Timing
Figure 25.12 DRAM
Cycle (Normal Mode,
1 Wait, TPC=0,
RCD=0)
763 Figure amended
Tcw1 Tc2
t
CASD1
t
CAC
t
RAC
t
AA
t
RDS
Column address
Figure 25.13 DRAM
Cycle (Normal Mode,
2 Waits, TPC=1,
RCD=1)
764 Figure amended
Tcw1 Tcw2
t
CASD1
t
CAC
t
AA
Column address