Datasheet

115
Table 6.5 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module IRQ Notes
DMAC/DTC active
judgment
0 or 1 1 1 state required for interrupt
signals for which
DMAC/DTC activation is
possible
Compare identified inter-
rupt priority with SR mask
level
23
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0) The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
5 + m1 + m2 + m3 Performs the PC and SR
saves and vector address
fetch.
Interrupt Total: 7 + m1 + m2 + m3 9 + m1 + m2 + m3
response
Minimum: 10 12 0.35–0.42 µs at 28.7 MHz
time
Maximum: 12 + 2 (m1 + m2 +
m3) + m4
13 + 2 (m1 + m2 +
m3) + m4
0.67–0.70 µs at 28.7 MHz
*
Note: * When m1 = m2 = m3 = m4 = 1
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine