Datasheet

111
• Bits 7–0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt
request status.
Bits 7-0:
IRQ0F–IRQ7F Detection Setting Description
0 Level detection No IRQn interrupt request exists.
Clear conditions: When IRQn input is high level
Edge detection No IRQn interrupt request was detected. (initial value)
Clear conditions:
1. When a 0 is written after reading IRQnF = 1 status
2. When IRQn interrupt exception processing has been
executed
3. When a DTC transfer due to IRQn interrupt has been
executed
1 Level detection An IRQn interrupt request exists.
Set conditions: When IRQn input is low level
Edge detection An IRQn interrupt request was detected.
Set conditions: When a falling edge occurs at an IRQn input
IRQ pin
Edge
detection
Selection
CPU
interrupt

request
DTC
activation
request
Judgment
(IRQn interrupt acceptance/DTC transfer completion/IRQnF = 0 write after IRQnF = 1 read)
S
R
RESIRQn
Q
IRQnS
(0: level,
1: edge)
ISR.IRQnF
Level
detection
DTC
Figure 6.2 External Interrupt Process