Datasheet

106
Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Vector
Interrupt Priority
Interrupt Source
Vector
No.
Vector Table
Address
Offset
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
within IPR
Setting
Range
Default
Priority
MTU3 TGI3A 112 H'000001C0–
H'000001C3
0–15 (0) IPRE
(7–4)
High High
TGI3B 113 H'000001C4–
H'000001C7
0–15 (0)
TGI3C 114 H'000001C8–
H'000001CB
0–15 (0)
TGI3D 115 H'000001CC–
H'000001CF
0–15 (0)
Low
TCI3V 116 H'000001D0–
H'000001D3
0–15 (0) IPRE
(3–0)
—
MTU4 TGI4A 120 H'000001E0–
H'000001E3
0–15 (0) IPRF
(15–12)
High
TGI4B 121 H'000001E4–
H'000001E7
0–15 (0)
TGI4C 122 H'000001E8–
H'000001EB
0–15 (0)
TGI4D 123 H'000001EC–
H'000001EF
0–15 (0)
Low
TCI4V 124 H'000001F0–
H'000001F3
0–15 (0) IPRF
(11–8)
High
Reserved 125 H'000001F4–
H'000001F7
0–15 (0)
Low
SCI0 ERI0 128 H'00000200–
H'00000203
0–15 (0) IPRF
(7–4)
High
RXI0 129 H'00000204–
H'00000207
0–15 (0)
TXI0 130 H'00000208–
H'0000020B
0–15 (0)
TEI0 131 H'0000020C–
H'0000020F
0–15 (0)
Low Low