Datasheet

105
Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Vector
Interrupt Priority
Interrupt Source
Vector
No.
Vector Table
Address
Offset
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
within IPR
Setting
Range
Default
Priority
MTU0 TGI0A 88 H'00000160–
H'00000163
0–15 (0) IPRD
(15–12)
High High
TGI0B 89 H'00000164–
H'00000167
0–15 (0)
TGI0C 90 H'00000168–
H'0000016B
0–15 (0)
TGI0D 91 H'0000016C–
H'0000016F
0–15 (0)
Low
TCI0V 92 H'00000170–
H'00000173
0–15 (0) IPRD
(11–8)
—
MTU1 TGI1A 96 H'00000180–
H'00000183
0–15 (0) IPRD
(7–4)
High
TGI1B 97 H'00000184–
H'00000187
0–15 (0)
Low
TCI1V 100 H'00000190–
H'00000193
0–15 (0) IPRD
(3–0)
High
TCI1U 101 H'00000194–
H'00000197
0–15 (0)
Low
MTU2 TGI2A 104 H'000001A0–
H'000001A3
0–15 (0) IPRE
(15–12)
High
TGI2B 105 H'000001A4–
H'000001A7
0–15 (0)
Low
TCI2V 108 H'000001B0–
H'000001B3
0–15 (0) IPRE
(11–8)
High
TCI2U 109 H'000001B4–
H'000001B7
0–15 (0)
Low Low