Datasheet

73
RES = 0
Power-on reset state Manual reset state
Sleep mode Standby mode
Program execution state
Bus release state
Exception processing state
RES = 1
MRES = 1
RES = 1
When an interrupt source
or DMA address error occurs
NMI interrupt
source occurs
Exception 
processing
ends
Bus request
generated
Exception
processing
source occurs
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
SBY bit set 
for SLEEP 
instruction
From any state
when RES = 0
From any state when
RES = 1 and MRES = 0
Reset states
Power-down state
Bus request
generated
Bus request
cleared
Figure 2.6 Transitions between Processing States
Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset
results. When the RES pin is high and MRES is low, a manual reset will occur.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.