To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 32 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series (CPU Core SH-2) Rev.6.00 2003.
Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/ SH7040 Series (CPU Core SH-2) SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual REJ09B0044-0600O
Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Preface The SH7040 Series (SH7040, SH7041, SH7042, SH7043, SH7044, SH7045) single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas Technology-original RISC CPU core with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power.
List of Items Revised or Added for This Version Section Page 1.1.1 SH7040 Series 7, Features 9 Description Type A/D Mask On-chip External Accuracy Bus Width (5Vversion) Package Abbreviation Version ROM ZTAT SH7042 Notes on the SH7040 Series Specifications SH7042A Frequency Voltage Type Name ROM Electrical Characteristics 128 kB 16 bits ±15LSB QFP2020-112 –20°C to 75°C 28 MHz (High-Speed) 16 MHz 5V 3.
Section Page Description 11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0– DMATCR3) 220 Description amended 11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) 221 The data for the upper 8 bits of a DMATCR is 0 Description amended • Bits 31–21—Reserved bits: Data are 0 value always be 0. 224 226 Description amended 233 337 Figure 12.55 Example of Output Phase Switching by External Input (1) Figure amended Figure amended TCLKC Figure 12.
Section Page Description 12.9.2 Block Diagram 444 Note added TIOC3B* Figure 12.125 POE Block Diagram TIOC3D* TIOC4A* TIOC4C* TIOC4B* TIOC4D* Note: * Includes multiplexed pins. 12.11.5 Usage Notes 453 Section added 14.2.8 Bit Rate Register (BRR) 491 Table amended Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) 27.0336 Bit Rate (Bits/s) n N Error (%) 110 3 119 0.00 150 3 87 0.00 300 2 175 0.00 600 1 87 0.00 1200 1 175 0.00 2400 1 87 0.
Section Page Description 15.4.9 A/D Conversion Time 562 33 MHz deleted 564 Figure amended Table 15.8 Operating Frequency and CKS Bit Settings 15.6 Notes on Use Figure 15.14 Example of a Protection Circuit for the Analog Input Pins AVcc AVref This LSI 100Ω Rin*2 AN0 to AN7 *1 0.1µF *1 AVss Notes: Numbers are only to be noted as reference value *1 10µF 0.01µF *2 Rin: Input impedance 16.7.
Section Page 21.2.2 Socket 672 Adapter Pin Correspondence and Memory Map Description Figure amended 2 nF Figure 21.3 SH7042 Pin and HN27C101 Pin Correspondence (120-Pin Version) 100 Ω 0.1 µF Figure 21.4 SH7043 673 Pin and HN27C101 Pin Correspondence (144-Pin Version) Figure amended 2 nF 100 Ω 0.1 µF 22.2.2 Mode Transition Diagram Figure 22.
Section Page Description 22.7.2 ProgramVerify Mode 706 Figure amended Start Figure 22.
Section Page Description 22.7.4 Erase-Verify Mode 713 Figure amended Start Figure 22.
Section Page Description 25.2 DC Characteristics 751 Note amended *2 5 mA in the A mask version, except for F-ZTAT products. Table 25.2 DC Characteristics 25.3.2 Control Signal Timing 754 Note: * The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but when thesetup times shown here are provided, the signals are considered to have produced changes at clock rise (for RES, MRES, BREQ) or clock fall (for NMI and IRQ7–IRQ0).
Section Page Description 25.3.3 Bus Timing 764 Figure amended Figure 25.14 DRAM Cycle (Normal Mode, 3 Waits, TPC=1, RCD=1) Tcw1 Tcw2 Column tCASD1 tCAC tAA 25.3.5 Multifunction Timer Pulse Unit Timing 770 Figure 25.23 MTU I/O Timing Figure 25.24 MTU Clock Input Timing Figure amended tTOCD 770 Figure amended tTCKS 25.3.11 Measuring Conditions for AC Characteristics Figure 25.
Section Page Description 25.4 A/D Converter Characteristics 779 Table amended Non-linearity error * Table 25.16 A/D Converter Timing (A mask) Offset error* Full scale error* Quantize error * 26.2 DC Characteristics 782 Table amended VCC× 0.07 Schmitt PA2, PA5, PA6– VT+ – VT– trigger input PA9, voltage PE0–PE15 Table 26.2 DC Characteristics 783 — — V VT + ≥ VCC× 0.9V (min) VT – ≤ VCC× 0.2V (max) Table amended Analog supply current AI CC — 4 8 AI ref — 0.5 1* mA f = 16.
Section Page Description 26.3.3 Bus Timing 796 Figure amended Figure 26.13 DRAM Cycle (Normal Mode, 2 Waits, TPC = 1, RCD = 1) Tcw1 Tcw2 Column address tCASD1 tCAC tAA tRAC tCASD1 Figure 26.14 DRAM 796 Cycle (Normal Mode, 3 Waits, TPC = 1, RCD = 1) Figure amended Tcw1 Tcw2 Column address tCASD1 tCAC tAA tRAC tCASD1 26.3.5 Multifunction Timer Pulse Unit Timing 802 Figure amended CK Figure 26.23 MTU I/O Timing tTOCD Output compare output 26.3.
Section Page Description Appendix B Block Diagrams 844 Note added On-chip flash memory* Figure B.19 PB4/IRQ2/POE2/ CASH,PB3/IRQ1/ POE1/CASL Block Diagram (F-ZTAT Version) Appendix C Pin States A17 Note: * Only when n = 4. 865 Table amended Pin modes Table C.
Section Page Description Appendix C Pin States 866 Table amended Pin modes Table C.
Section Page Description Appendix C Pin States 867 Table amended Pin modes Table C.
Section Page Description Appendix C Pin States 868 Table amended Pin modes Table C.
Section Page Description Appendix E Product 876, 877 Code Lineup Table amended Product Type Mask Version Table E.
Contents Section 1 1.1 1.2 1.3 1.4 SH7040 Series Overview ............................................................................. SH7040 Series Overview................................................................................................... 1.1.1 SH7040 Series Features........................................................................................ Block Diagram...................................................................................................................
4.3 4.4 4.5 4.2.2 External Clock Input Method ............................................................................... Prescaler............................................................................................................................. Oscillator Halt Function..................................................................................................... Usage Notes ................................................................................................................
6.3 6.4 6.5 6.6 6.2.3 IRQ Interrupts....................................................................................................... 6.2.4 On-Chip Peripheral Module Interrupts................................................................. 6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. Description of Registers..................................................................................................... 6.3.
Section 8 8.1 8.2 8.3 8.4 Overview............................................................................................................................ 8.1.1 Features................................................................................................................. 8.1.2 Block Diagram...................................................................................................... 8.1.3 Register Configuration ......................................................................
9.4.4 Cache Hit after Cache Miss .................................................................................. 162 Section 10 Bus State Controller (BSC) ......................................................................... 163 10.1 Overview............................................................................................................................ 10.1.1 Features................................................................................................................. 10.1.
11.2 11.3 11.4 11.5 11.1.2 Block Diagram...................................................................................................... 11.1.3 Pin Configuration ................................................................................................. 11.1.4 Register Configuration ......................................................................................... Register Descriptions.....................................................................................................
12.3 12.4 12.5 12.6 12.7 12.2.1 Timer Control Register (TCR) ............................................................................. 12.2.2 Timer Mode Register (TMDR)............................................................................. 12.2.3 Timer I/O Control Register (TIOR) ..................................................................... 12.2.4 Timer Interrupt Enable Register (TIER)............................................................... 12.2.5 Timer Status Register (TSR) ..
12.8 12.9 12.10 12.11 12.7.7 Contention between TGR Write and Input Capture ............................................. 12.7.8 Contention between Buffer Register Write and Input Capture ............................ 12.7.9 Contention between TGR Write and Compare Match ......................................... 12.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 12.7.11 Counter Value during Complementary PWM Mode Stop ................................... 12.7.
13.1 Overview............................................................................................................................ 13.1.1 Features................................................................................................................. 13.1.2 Block Diagram...................................................................................................... 13.1.3 Pin Configuration .................................................................................................
14.4 SCI Interrupt Sources and the DMAC/DTC...................................................................... 14.5 Notes on Use ...................................................................................................................... 14.5.1 TDR Write and TDRE Flags ................................................................................ 14.5.2 Simultaneous Multiple Receive Errors................................................................. 14.5.3 Break Detection and Processing..
16.2 16.3 16.4 16.5 16.6 16.7 16.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 16.2.1 A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1) ............ 16.2.2 A/D Control/Status Register (ADCSR0, ADCSR1)............................................. 16.2.3 A/D Control Register (ADCR0, ADCR1) ...................
18.3.1 Port A I/O Register H (PAIORH)......................................................................... 18.3.2 Port A I/O Register L (PAIORL) ......................................................................... 18.3.3 Port A Control Register H (PACRH) ................................................................... 18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ................................. 18.3.5 Port B I/O Register (PBIOR).....................................................
Section 21 128kB PROM................................................................................................... 669 21.1 Overview............................................................................................................................ 669 21.2 PROM Mode...................................................................................................................... 670 21.2.1 PROM Mode Settings...................................................................................
22.8.3 Error Protection .................................................................................................... 22.9 Flash Memory Emulation in RAM .................................................................................... 22.10 Note on Flash Memory Programming/Erasing .................................................................. 22.11 Flash Memory Programmer Mode..................................................................................... 22.11.
25.3.9 High-speed A/D Converter Timing (excluding A mask) ..................................... 25.3.10 Mid-speed Converter Timing (A mask) ............................................................... 25.3.11 Measuring Conditions for AC Characteristics ..................................................... 25.4 A/D Converter Characteristics........................................................................................... 774 776 778 779 Section 26 Electrical Characteristics (3.3V, 16.
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Section 1 SH7040 Series Overview 1.1 SH7040 Series Overview The SH7040 Series (SH7040/41/42/43/44/45) CMOS single-chip microprocessors integrate a Renesas-original architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power.
• • • • Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Delayed branch instructions reduce pipeline disruption during branch Instruction set based on C language Instruction execution time: one instruction/cycle (35 ns/instruction at 28.
• • • • Outputs chip-select signals for each area During DRAM space access: • Outputs RAS and CAS signals for DRAM • Can generate a RAS precharge time assurance Tp cycle DRAM burst access function Supports high-speed access mode for DRAM DRAM refresh function Programmable refresh interval Supports CAS-before-RAS refresh and self-refresh modes Wait cycles can be inserted using an external WAIT signal Address data multiplex I/O devices can be accessed Direct Memory Access Controller (DMAC) (4 Cha
• • • • • • • • 16 independent comparators 8 types of counter input clock Input capture function Pulse output mode One shot, toggle, PWM, phase-compensated PWM, reset-synchronized PWM Multiple counter synchronization function Phase-compensated PWM output mode Non-overlapping waveform output for 6-phase inverter control Automatic setting for dead time PWM duty cycle can be set from 0 to 100% Output off function Reset-synchronized PWM mode 3-phase output of any duty cycle positive phase/reverse
Total: 82 • QFP 144 (SH7041, SH7043, SH7045) Input/output: 98 Input: 8 Total: 106 A/D Converter: • • • • 10 bits × 8 channels Conversion upon external trigger possible Sample and hold function: two on-chip units (two channels can be sampled simultaneously) Depending on the product, there is a high speed, mid-accuracy A/D on-chip type and a midspeed, high accuracy A/D on-chip type. For details, see the product lineup.
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Type Abbreviation ZTAT SH7042 SH7042A Mask Version A mask SH7043 FLASH MASK A/D On-chip External Accuracy ROM Bus Width (5V Version) Package Notes on the SH7040 Series Specifications (For details, see each section in this manual) Operating Temp 128 kB 16 bits ±15LSB QFP2020-112 (High-Speed) 128 kB 16 bits ±4LSB QFP2020-112 –20°C to 75°C (Mid-Speed) TQFP1414-120 QFP2020-112Cu* 128 kB 32 bits ±15LSB QFP2020-144 (High-Speed) Frequency Voltage Type Name –20°C to 75°C 28 MHz 16 MHz INTC D
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Notes on the SH7040 Series Specifications (For details, see each section in this manual) Type Abbreviation Mask Version A/D On-chip External Accuracy ROM Bus Width (5V Version) Package MASK SH7044 A mask 256 kB 16 bits ±4LSB QFP2020-112 (Mid-Speed) –20°C to 75°C 28 MHz 5V HD6437044F28 Change the interrupt Change the DTER Change the setting Change the Usage See “Midvectors related A/D access methods methods on transfer Notes Speed A/D converter and DTC vectors requests Converter” See “256 kB M
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1.
: Peripheral address bus ;;;;; ;;;;;: Peripheral data bus : Internal address bus ;;;;; : Internal upper data bus ;;;;; ;;;;; ;;;;;: Internal lower data bus PE15/TIOC4D/DACK1/IRQOUT PE14/TIOC4C/DACK0/AH PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE10/TIOC3C PE9/TIOC3B PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1 PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0 ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; ;;; ;;;;;;;;
1.3 Pin Arrangement and Pin Functions 1.3.
PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 Vss PE4/TIOC1A PE3/TIOC0D/DRAK1 PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0 NC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D Vss PE10/TIOC3C PE9/TIOC3B PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A Vcc NC PE5/TIOC1B Vss AVcc PF7/AN7 PF6/AN6 AVss Figure 1.4 shows the pin arrangement for the TFP-120 (top view).
QFP-144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PD16/D16/IRQ0 VSS PD17/D17/IRQ1 PD18/D18/IRQ2 PD19/D19/IRQ3 PD20/D20/IRQ4 PD21/D21/IRQ5 PD22/D22/IRQ6 PD23/D23/IRQ7 VCC PD24/D24/DREQ0 VSS PD25/D25/DREQ1 PD26/D26/DACK0 PD27/D27/DACK1 PD28/D28/CS2 PD29/D29/CS3 VSS PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10/CS0 PA11/CS1 PA12/WRL PA13/WRH PD30/D30/IRQOUT PD31/D31/ADTRG WDTOVF PA14/RD VSS PB9/IRQ7/A21/ADTRG VCC PB8/IRQ6/A20/
1.3.2 Table 1.2 Pin Arrangement by Mode Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) Pin No.
Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No.
Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No.
Table 1.2 Pin Arrangement by Mode for SH7040, SH7042 (QFP-112 Pin) (cont) Pin No.
Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) TQFP120 Pin No.
Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No.
Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No.
Table 1.3 Pin Arrangement by Mode for SH7040, SH7042 (TQFP-120 Pin) (cont) TQFP120 Pin No.
Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) Pin No.
Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No.
Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No.
Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No.
Table 1.4 Pin Arrangement by Mode for SH7041, SH7043 (QFP-144 Pin) (cont) Pin No.
Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) PinNo.
Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo.
Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo.
Table 1.5 Pin Arrangement by Mode for SH7044 (QFP-112 Pin) (cont) PinNo.
Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) PinNo.
Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo.
Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo.
Table 1.6 Pin Arrangement by Mode for SH7045 (QFP-144 Pin) (cont) PinNo.
1.3.3 Pin Functions Table 1.7 lists the pin functions. Table 1.7 Pin Functions Classification Symbol I/O Name Function Power supply VCC I Supply Connects to power supply. Connect all V CC pins to the system supply. No operation will occur if there are any open pins. VSS I Ground Connects to ground. Connect all V SS pins to the system ground. No operation will occur if there are any open pins. VPP I Program supply Connects to the power supply (VCC) during normal operation.
Table 1.7 Pin Functions (cont) Classification Symbol I/O Name Function Operating mode control MD0–MD3 I Mode set Determines the operating mode. Do not change input value during operation. FWP I Flash memory write protect Protects flash memory from being written or deleted. NMI I Non-maskable interrupt Non-maskable interrupt request pin. Enables selection of whether to accept on the rising or falling edge. IRQ0– IRQ7 I Interrupt requests 0–7 Maskable interrupt request pins.
Table 1.7 Pin Functions (cont) Classification Symbol I/O Name Function Bus control (cont) CASL O Lower column address strobe Timing signal for DRAM column address strobe. Output when the lower 8 bits of data are accessed. Bus control multifunction timer/pulse unit RDWR O DRAM read/write DRAM write strobe signal. AH O Address hold Address hold timing signal for devices using an address/data multiplex bus.
Table 1.7 Pin Functions (cont) Classification Symbol I/O Name Function Bus control multifunction timer/pulse unit (cont) TIOC3A I/O MTU input capture/output compare (channel 3) Channel 3 input capture input/output compare output/PWM output pins. I/O MTU input capture/output compare (channel 4) Channel 4 input capture input/output compare output/PWM output pins. DREQ0– DREQ1 I DMA transfer request (channels 0, 1) Input pin for external requests for DMA transfer.
Table 1.7 Pin Functions (cont) Classification Symbol I/O Name Function I/O ports POE0– POE3 I Port output enable Input pin for port pin drive control when general use ports are established as output. PA0– PA15 (QFP-112) I/O General purpose port General purpose input/output port pins. Each bit can be designated for input/output. PA0– PA23 (QFP-144) PB0–PB9 I/O General purpose port General purpose input/output port pins. Each bit can be designated for input/output.
1.4 The F-ZTAT Version Onboard Programming There are 2 modes on the F-ZTAT version: a mode that writes and overwrites programs using the special writer and a mode that writes and overwrites programs onboard the application system. When rebooting after setting each mode pin and FWP pin during the reset condition, the microcomputer will transfer to one of the modes indicated in figure 1.6. In the user mode, data can be read from the flash memory but cannot be written or deleted.
Write control program Application program Boot program RXD1 TXD1 SCI 1 Write control program area Application program Boot program area Figure. 1.
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Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0–R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP).
2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.
2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows a system register.
2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 0 Longword Figure 2.4 Longword Operand 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords.
Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
Table 2.3 Delayed Branch Instructions SH7040 Series CPU Description Example of Conventional CPU BRA TRGET ADD.W ADD R1,R0 Executes an ADD before branching to TRGET R1,R0 BRA TRGET Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation operations are executed in two to three cycles.
Table 2.5 Immediate Data Accessing Classification SH7040 Series CPU Example of Conventional CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 .DATA.W H'1234 MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0 ................. 32-bit immediate ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data.
2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Addresses Calculation Direct register addressing Rn The effective address is register Rn. (The operand is the contents of register Rn.) — Indirect register addressing @Rn The effective address is the content of register Rn.
Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation Indirect register addressing with displacement @(disp:4, Rn) The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation.
Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR addressing GBR + Equation GBR + R0 GBR + R0 R0 PC relative addressing with displacement @(disp:8, PC) The effective address is the PC value plus an 8-bit displacement (disp). The value of disp is zeroextended, and is doubled for a word operation, and quadrupled for a longword operation.
Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mode Instruction Format Effective Addresses Calculation PC relative addressing disp:8 The effective address is the PC value sign-extended with an 8-bit displacement (disp), doubled, and added to the PC value. Equation PC + disp × 2 PC disp (sign-extended) + PC + disp × 2 × 2 disp:12 The effective address is the PC value sign-extended with a 12-bit displacement (disp), doubled, and added to the PC value.
2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • • • • • xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table 2.
Table 2.9 Instruction Formats (cont) Source Operand Destination Operand Instruction Formats nm format 15 0 xxxx nnnn mmmm xxxx md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx 0 nnnn nnnn: Direct register ADD Rm,Rn mmmm: Direct register nnnn: Indirect register MOV.L Rm,@Rn mmmm: Indirect post-increment register (multiply/ accumulate) nnnn* : Indirect post-increment register (multiply/ accumulate) MACH, MACL MAC.
Table 2.
2.4 Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer Arithmetic operations 5 21 No.
Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function No.
Table 2.10 Classification of Instructions (cont) Operation Classification Types Code Function No. of Instructions System control 31 Total: 11 62 CLRT T bit clear CLRMAC MAC register clear LDC Load to control register LDS Load to system register NOP No operation RTE Return from exception processing SETT T bit set SLEEP Shift into power-down mode STC Storing control register data STS Storing system register data TRAPA Trap exception handling 142 Table 2.
Table 2.11 Instruction Code Format Item Format Explanation Instruction OP.Sz SRC,DEST OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* 1 Instruction code MSB ↔ LSB mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 . . .
Table 2.12 Data Transfer Instructions Execution Cycles T Bit Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii #imm → Sign extension → Rn 1 — MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1 — MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1 — MOV 0110nnnnmmmm0011 Rm → Rn 1 — MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 — MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1 — MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1 — MOV.
Table 2.12 Data Transfer Instructions (cont) Instruction Instruction Code Operation Execution Cycles MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign extension → Rn 1 — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign extension → Rn 1 — MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 — MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1 — MOV.
Table 2.
Table 2.13 Arithmetic Operation Instructions (cont) Execution Cycles T Bit Instruction Instruction Code Operation DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit 2 to 4 * — DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit 2 to 4 * — DT Rn 0100nnnn00010000 Rn – 1 → Rn, when Rn 1 is 0, 1 → T. When Rn is nonzero, 0 → T Comparison result EXTS.
Table 2.13 Arithmetic Operation Instructions (cont) Instruction Instruction Code Operation Execution Cycles SUB Rm,Rn 0011nnnnmmmm1000 Rn–Rm → Rn 1 — SUBC Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T → Rn, Borrow → T 1 Borrow SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Overflow T Bit Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.
Table 2.14 Logic Operation Instructions Instruction Instruction Code Operation Execution Cycles AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 — AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 — AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → (R0 + GBR) 3 — NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 — OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 — OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 — OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → (R0 + GBR) 3 — TAS.
Table 2.
Table 2.16 Branch Instructions Exec.
Table 2.17 System Control Instructions Instruction Instruction Code Operation Exec. Cycles T Bit CLRT 0000000000001000 0→T 1 0 CLRMAC 0000000000101000 0 → MACH, MACL 1 — LDC Rm,SR 0100mmmm00001110 Rm → SR 1 LSB LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1 — LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1 — LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3 LSB LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3 — LDC.
Table 2.17 System Control Instructions (cont) Instruction Instruction Code Operation Exec. Cycles T Bit STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1 — STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1 — STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn) 1 — TRAPA #imm 11000011iiiiiiii PC/SR → stack area, 8 — (imm × 4 + VBR) → PC Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums.
From any state when RES = 0 From any state when RES = 1 and MRES = 0 Power-on reset state Manual reset state RES = 0 RES = 1 When an interrupt source or DMA address error occurs RES = 1 MRES = 1 Reset states Exception processing state Bus request cleared NMI interrupt source occurs Bus request generated Exception processing source occurs Bus release state Bus request generated Bus request generated Bus request cleared Bus request cleared SBY bit cleared for SLEEP instruction Sleep mode Excep
For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area.
CPU returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. In this mode, power consumption drops markedly, since the oscillator stops (table 2.18). Table 2.
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Section 3 Operating Modes 3.1 Operating Modes, Types, and Selection This LSI has five operating modes and three clock modes, determined by the setting of the mode pins (MD3–MD0). Do not change the mode pin settings during LSI operation (while power is on). (In the F-ZTAT version, however, MD1 can be changed in the power-on reset state.) Table 3.1 indicates the setting method for the operating mode. Table 3.1 Operating Mode Setting Pin Setting Mode Mode No.
Table 3.2 indicates the setting method for the clock mode. Table 3.2 Clock Mode Setting MD3 MD2 Clock Mode 0 0 PLL ON × 1 0 1 PLL ON × 2 1 0 PLL ON × 4 1 1 Reserved (PROM mode only) 3.2 Explanation of Operating Modes Table 3.3 describes the operating modes. Table 3.3 Operating Modes Mode Description (MCU) Mode 0 CS0 area becomes an external memory space with 8-bit bus width for the 112-pin version, and 16-bit for the 144-pin version.
3.3 Pin Configuration Table 3.4 describes the function of each operating mode related pin. Table 3.
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Section 4 Clock Pulse Generator (CPG) 4.1 Overview The SH7040 Series has an on-chip clock pulse generator (CPG) that generates the system clock (φ), as well as the internal clock (φ/2 to φ/8192). The CPG consists of an oscillator, a PLL, and a prescaler. 4.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 4.1. PLLCAP CK EXTAL Oscillator PLL circuit XTAL Prescaler MD2 MD3 Clock mode control circuitry φ φ/2 to φ/8192 Within the LSI Figure 4.
CL1 EXTAL 4–10 MHz CL2 XTAL Rd CL1 = CL2 = 18–22 pF (Recommended value) Figure 4.2 Connection of the Crystal Oscillator (Example) Table 4.1 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter 4 8 10 Rd (Ω) 500 200 0 Crystal Oscillator: Figure 4.3 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 4.2. L CL Rs XTAL EXTAL Co Figure 4.3 Crystal Oscillator Equivalent Circuit Table 4.
When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to delay until after the oscillation stabilization time (upon power-on) or after release from standby, in order to ensure the PLL stabilization time. EXTAL XTAL External clock input 4–10 MHz Open Figure 4.4 Example of External Clock Connection 4.
4.5.2 Notes on Board Design When connecting a crystal oscillator, observe the following precautions: • To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry. • When designing the board, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Figure 4.5 shows the precautions regarding oscillator block board settings. Crossing of signal lines prohibited CL1 XTAL CL2 EXTAL Figure 4.
External circuitry such as that shown in figure 4.6 is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP Rp: 200 Ω PLLVCC CPB: 0.1 µF* PLLVSS VCC CB: 0.1 µF* VSS Note: * CB and CPB are laminated ceramic capacitors (Recommended values) Figure 4.6 Cautions for Use of PLL Oscillator Circuit Place oscillation stabilization capacitor C1 and resistor R1 near the PLLCAP pin, and ensure that these lines do not cross any other signal lines. Supply the C1 ground from PLLVSS .
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 5.
5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and the Start of Exception Processing Exception Source Timing of Source Detection and Start of Processing Reset Power-on reset Starts when the RES pin changes from low to high. Manual reset Starts when the RES pin is high and the MRES pin changes from low to high.
5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated.
Table 5.
Table 5.5 Types of Resets Conditions for Transition to Reset Status Internal Status Type RES MRES CPU On-Chip Peripheral Module Power-on reset Low — Initialized Initialized Manual reset High Low Initialized Not initialized 5.2.1 Power-On Reset When the RES pin is driven low, the LSI does a power-on reset.
reset mode. (Keep at low level for at least the longest bus cycle.) See Appendix C, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate the same as described for power-on resets. 5.3 Address Errors Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.
5.3.1 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3.
5.4.1 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt priority level is 15.
Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instructions TRAPA — Illegal slot instructions Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Undefined code anywhere besides in a delay slot — General illegal instructions 5.5.
5.5.3 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. 5.
5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.11. Table 5.
5.8 Notes on Use 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.
Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.
IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 UBC DMAC MTU CMT SCI A/D DTC WDT BSC I/O Input control CPU/ DTC request judgment Priority ranking judgment Comparator Interrupt request SR (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 CPU DTER ICR DTC IPR ISR Module bus Bus interface INTC UBC: DMAC: MTU: CMT: SCI: A/D: DTC: WDT:
6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0–IRQ7 I Input of maskable interrupt request signals Interrupt request output pin IRQOUT O Output of notification signal when an interrupt has occurred 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2.
6.2 Interrupt Sources There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge.
6.2.
Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Setting Default Range Priority Interrupt Source Vector No.
Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Address Offset Interrupt Priority (Initial Value) Interrupt Source Vector No.
Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Address Offset Interrupt Priority (Initial Value) Interrupt Source Vector No.
Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont) Interrupt Vector Vector Table Address Offset Interrupt Priority (Initial Value) Interrupt Source Vector No.
6.3 Description of Registers 6.3.1 Interrupt Priority Registers A–H (IPRA–IPRH) Interrupt priority registers A–H (IPRA–IPRH) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA–IPRH bits is shown in table 6.4.
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4, and 3–0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F.
• Bit 8—NMI Edge Select (NMIE) Bit 8: NMIE Description 0 Interrupt request is detected on falling edge of NMI input (initial value) 1 Interrupt request is detected on rising edge of NMI input • Bits 7–0—IRQ0–IRQ7 Sense Select (IRQ0S–IRQ7S): These bits set the IRQ0–IRQ7 interrupt request detection mode. Bits 7-0: IRQ0S–IRQ7S Description 0 Interrupt request is detected on low level of IRQ input (initial value) 1 Interrupt request is detected on falling edge of IRQ input 6.3.
• Bits 7–0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt request status. Bits 7-0: IRQ0F–IRQ7F Detection Setting Description 0 Level detection No IRQn interrupt request exists. Clear conditions: When IRQn input is high level Edge detection No IRQn interrupt request was detected. (initial value) Clear conditions: 1. When a 0 is written after reading IRQnF = 1 status 2. When IRQn interrupt exception processing has been executed 3.
6.4 Interrupt Operation 6.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers A–H (IPRA–IPRH). Lower-priority interrupts are ignored.
Program execution state Interrupt? No Yes No NMI? Yes User break? Yes No Level 15 interrupt? No IRQOUT = low level*1 Yes Save SR to stack Yes Save PC to stack I3 to I0 ≤ level 14? No Copy accept-interrupt level to I3 to I0 Yes IRQOUT = high level*2 Level 14 interrupt? No Yes Level 1 interrupt? I3 to I0 ≤ level 13? Yes No Yes No I3 to I0 = level 0? No Reads exception vector table Branches to exception service routine I3 to I0: Interrupt mask bits of status register Notes: *1 *2 IRQ
6.4.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 PC*1 32 bits 4n–4 SR 32 bits SP*2 4n Notes: *1 *2 PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing 6.5 Interrupt Response Time Table 6.
Table 6.5 Interrupt Response Time Number of States NMI, Peripheral Module IRQ Notes DMAC/DTC active judgment 0 or 1 1 1 state required for interrupt signals for which DMAC/DTC activation is possible Compare identified interrupt priority with SR mask level 2 3 Wait for completion of sequence currently being executed by CPU X (≥ 0) Item The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4).
Interrupt acceptance 1 5 + m1 + m2 + m3 3 m1 m2 1 m3 1 3 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch F D E E M M E M E E F Interrupt service routine start instruction F D E F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding).
Interrupt source Interrupt source flag clear (by DMAC) DMAC Interrupt source (those not designated as DMAC activating sources) CPU interrupt request DTC activation request DTER Interrupt source flag clear (by DTC) DTE clear DTECLR Transfer end Figure 6.6 Interrupt Control Block Diagram 6.6.1 Handling DTC Activating and CPU Interrupt Sources, but Not DMAC Activating Sources 1. 2. 3. 4. Either do not select the DMAC as a source, or clear the DME bit to 0.
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt or DTC Activating Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources and DTC activating sources are masked regardless of the interrupt priority level register settings or DTC register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears activating sources at the time of data transfer. 6.6.
Section 7 User Break Controller (UBC) 7.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU, DMAC, or DTC. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs without using a large in-circuit emulator. 7.1.
UBBR UBAMRH UBARH UBAMRL UBARL Internal bus Bus interface Module bus Break condition comparator User break interrupt generating circuit UBC Interrupt request Interrupt controller UBARH, UBARL: User break address registers H, L UBAMRH, UBAMRL: User break address mask registers H, L UBBR: User break bus cycle register Figure 7.1 User Break Controller Block Diagram 7.1.3 Register Configuration The UBC has the five registers shown in table 7.1.
Table 7.1 Register Configuration Name Abbr. R/W Initial Value Address User break address register H UBARH R/W H'0000 H'FFFF8600 8, 16, 32 User break address register L UBARL R/W H'0000 H'FFFF8602 8, 16, 32 User break address mask register H UBAMRH R/W H'0000 H'FFFF8604 8, 16, 32 User break address mask register L UBAMRL R/W H'0000 H'FFFF8606 8, 16, 32 User break bus cycle register UBBR R/W H'0000 H'FFFF8608 8, 16, 32 7.2 Register Descriptions 7.2.
UBARL: Bit: UBARL Initial value: R/W: Bit: UBARL Initial value: R/W: 15 14 13 12 11 10 9 8 UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • UBARH Bits 15–0—User Break Address 31–16 (UBA31–UBA16): These bits store the upper bit values (bits 31–16) of the address of the break condition.
UBAMRL: Bit: UBAMRL Initial value: R/W: Bit: UBAMRL Initial value: R/W: 15 14 UBM15 13 UBM14 UBM13 12 11 UBM12 UBM11 10 9 8 UBM10 UBM9 UBM8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • UBAMRH Bits 15–0—User Break Address Mask 31–16 (UBM31–UBM16): These bits designate whether to mask any of the break address 31–16 bits (UBA31–UBA16) establ
Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bits 15–8—Reserved: These bits always read as 0. The write value should always be 0.
• Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles. Bit 3: RW1 Bit 2: RW0 Description 0 0 No user break interrupt occurs (initial value) 1 Break on read cycles 0 Break on write cycles 1 Break on both read and write cycles 1 • Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break condition.
7.3 Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR).
UBARH/UBARL UBAMRH/UBAMRL 32 32 Internal address bits 31–0 32 CP1 CP0 ID1 ID0 32 32 CPU cycle DMA/DTC cycle Instruction fetch User break interrupt Data access RW1 RW0 SZ1 SZ0 Read cycle Write cycle Byte size Word size Longword size Figure 7.
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in 1 bus cycle. Therefore, 2 instructions can be retrieved in 1 bus cycle when fetching instructions from on-chip memory. At such times, only 1 bus cycle is generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to cause independent breaks.
2. Register settings: Conditions set: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size not included in conditions) A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3.
7.4.3 Break on DMA/DTC Cycle 1. Register settings: Conditions set: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 Address: H'0076BCDC Bus cycle: DMA/DTC, data access, read, longword A user break interrupt occurs when longword data is read from address H'0076BCDC. 2.
Instruction execution: TRAPA instruction execution → Branch destination instruction execution 3.
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Section 8 Data Transfer Controller (DTC) 8.1 Overview The SH7040 Series has an on-chip data transfer controller (DTC), which is activated either by interrupts or software and can perform data transfers. 8.1.
8.1.2 Block Diagram Figure 8.1 shows the DTC block diagram. DTC transfer information is located in memory.
8.1.3 Register Configuration The DTC has five registers in memory used for storing transfer data: DTMR, DTCR, DTSAR, DTDAR, and DTIAR. It is controlled by the three registers DTER (DTEA–DTEE), DTCSR, and DTBR. The register configurations are listed in table 8.1. Table 8.1 Register Configuration *1 Name Abbr.
Bit: 15 14 13 12 11 10 9 8 SM1 SM0 DM1 DM0 MD1 MD0 SZ1 SZ0 Initial value: * * * * * * * * R/W: — — — — — — — — Bit: 7 6 5 4 3 2 1 0 DTS CHNE DISEL NMIM — — — — Initial value: * * * * * * * * R/W: — — — — — — — — Bit name: Note: * Initial value undefined. • Bits 15–14—Source Address Mode 1, 0 (SM1, SM0): These bits designate whether to hold, increment, or decrement the DTSAR after a data transfer.
• Bits 11–10—DTC Mode 1, 0 (MD1, MD0): These bits designate the DTC transfer mode. Bit 11 (MD1) Bit 10 (MD0) Description 0 0 Normal mode 0 1 Repeat mode 1 0 Block transfer mode 1 1 Reserved (setting prohibited) • Bits 9–8—DTC Data Transfer Size 1, 0 (SZ1, SZ0): These bits designate the data size for data transfers.
• Bit 5—DTC Interrupt Select (DISEL): This bit designates whether to prohibit or allow interrupt requests to the CPU after one-time DTC transfers.
Bit: 31 30 29 28 27 … 4 3 2 1 0 … Initial value: * * * * * … * * * * * R/W: — — — — — … — — — — — Note: * Initial value is undefined. 8.2.4 DTC Initial Address Register (DTIAR) The DTC initial address register (DTIAR) specifies the initial transfer source/transfer destination address in repeat mode.
Bit: 15 14 8 DTCRAH Initial value: * * * * * * * * R/W: — — — — — — — — Bit: 7 6 0 DTCRAL Initial value: * * * * * * * * R/W: — — — — — — — — Note: * Initial value is undefined. 8.2.6 DTC Transfer Count Register B (DTCRB) The DTCRB is a 16-bit register that designates the block length in block transfer mode. The contents of this register is located in memory.
For the A mask, overwrite this register as follows: When clearing bit to 0: read the 1 bit to clear and write 0. When setting bit to 1: read the 0 bit to set and write 1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * DTER bits can only be modified by writing 1 after reading 0, or writing 0 after reading 1. 8.2.
• Bit 10—NMI Flag Bit (NMIF): Indicates that an NMI interrupt has occurred. When the NMIF bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. If, however, a transfer has already started with the NMIM bit of the DTMR set to 1, execution will continue until that transfer ends. To clear the NMIF bit, read the 1 from it, then write a 0. The NMIF bit is initialized to 0 by power-on resets and in standby mode.
8.2.9 DTC Information Base Register (DTBR) The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory address containing DTC transfer information. Always access the DTBR in word or longword units. If it is accessed in byte units the register contents will become undefined at the time of a write, and undefined values will be read out upon reads. The DTBR is not initialized either by resets or in standby mode.
Start Initial settings DTMR, DTCR, DTIAR, DTSAR, DTDAR NMIF = AE = 0? No Yes Transfer request generated? No Yes DTC vector read Transfer information read DTCRA = DTCRA – 1 (normal/block transfer mode) DTCRAL = DTCRAL – 1 (repeat mode) Transfer (1 transfer unit) DTSAR, DTDAR update DTCRB = DTCRB – 1 (block transfer mode) NMIF • NMIM + AE = 1? No Block transfer mode and DTCRB ≠ 0? No Yes Transfer information write Transfer information write NMI or address error CHNE = 0? Yes CPU interrupt reques
8.3.2 Activating Sources The DTC performs write operations to the DTCSR with either interrupt sources or software as its activating sources. Each interrupt source is designated by specific DTER bits to determine whether it becomes an interrupt request to the CPU or a DTC activating source. When the DISEL bit is 1, an interrupt, established as the DTC activating source, is requested of the CPU after each data transfer in DRC.
Through DTC activation, a register information start address is read from the vector table, then register information placed in memory space is read from that register information start address. Always designate register information start addresses in multiples of four. DTBR Memory space Register information start address (upper 16 bits) DTC vector table DTC vector address Register information start address (lower 16 bits) Register information Figure 8.
Table 8.
Table 8.
Memory space Memory space Memory space DTMR DTCRA DTMR DTCRA DTMR DTCRA Register information start address DTIAR DTCRB Register information DTSAR DTSAR DTSAR DTDAR DTDAR DTDAR Normal mode Repeat mode Block transfer mode Figure 8.5 DTC Register Information Placement in Memory Space 8.3.5 Normal Mode Performs the transfer of one byte, one word, or one longword for each activation. The total transfer count is 1 to 65536.
The total transfer count is specified between 1 and 256. When the specified number of transfers ends, the address register of the designated repeat area is returned to its initial state and the transfer is repeated. Other address registers are consecutively incremented, decremented, or remain fixed. While DISEL = 0, no interrupt request is made to the CPU, even if the transfer with DTCRAL = 1 ends. Pulses for driving the stepping motor can be output. Table 8.4 shows the register functions for repeat mode.
Table 8.5 Block Transfer Mode Register Functions Values Written Back upon a Transfer Information Write Register Function DTMR Operation mode control DTMR DTCRA Transfer count DTCRA – 1 DTCRB Block length (Not written back) DTSAR Transfer source address (DTS = 0) Increment/ decrement/ fixed Transfer destination address (DTS = 0) DTDAR initial value DTDAR 8.3.8 (DTS = 1) DTSAR initial value (DTS = 1) Increment/ decrement/ fixed Operation Timing Figure 8.
Table 8.6 Execution State of DTC Mode Register Information Vector Read I Read/Write J Data Read K Data Write L Internal Operation M Normal 1 7 1 1 1 Repeat 1 7 1 1 1 Block transfer 1 7 N N 1 Note: N: block size (default set values of DTCRB) Table 8.
8.3.10 DTC Usage Procedure The procedure for DTC interrupt activation is as follows: 1. Transfer data (DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR) is located in memory space. 2. Establish the register information start address with DTBR and the DTC vector table. 3. Set the corresponding DTER bit to 1. 4. The DTC is activated when an interrupt source occurs. 5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER is not.
5. The RDRF flag of the SSR is set to 1 by each completion of a 1-byte data reception by the SCI, an RxI interrupt is generated, and the DTC is activated. The received data is transferred from RDR to RAM by the DTC, and the RDRF flag is 0 cleared. 6. After completion of 128 data transfers (DTCRA = 0), the DTER is cleared while the RDRF is maintained as 1, and an RxI interrupt request is made to the CPU. The interrupt processing routine clears the RDRF, and performs the other completion processing. 8.
Section 9 Cache Memory (CAC) 9.1 Overview The LSI has an on-chip cache memory (CAC) with 1 kbyte of cache data and a 256-entry cache tag. The cache data and cache tag space can be used as on-chip RAM space when the cache is not being used. 9.1.1 Features The CAC has the following features. The cache tag and cache data configuration is shown in figure 9.1.
9.1.2 Block Diagram Figure 9.2 shows a block diagram of the cache. CCR Cache tag Cache controller Cache data Internal data bus Internal address bus Cache Bus state controller External bus interface CCR: Cache control register Figure 9.2 Cache Block Diagram 9.1.3 Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space. The register configuration is shown in table 9.1.
Table 9.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size (Bits) Cache control register CCR R/W H'0000* H'FFFF8740 8, 16, 32 Note: * Bits 15–5 are undefined. 9.2 Register Explanation 9.2.1 Cache Control Register (CCR) The cache control register (CCR) selects the cache enable/disable of each space. The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is not initialized by manual resets or standby mode.
• Bit 3—CS3 Space Cache Enable (CECS3): Selects whether to use CS3 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 3 (CECS3) Description 0 CS3 space cache disabled (initial value) 1 CS3 space cache enabled • Bit 2—CS2 Space Cache Enable (CECS2): Selects whether to use CS2 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Table 9.2 Special Cache Space Space Classification Address Size Bus Width Address array H'FFFFF000–H'FFFFF3FF 1 kbyte 32 bit Data array H'FFFFF400–H'FFFFF7FF 1 kbyte 32 bit 9.3.1 Cache Address Array Read/Write Space The cache address array has a compulsory read/write (figure 9.3).
9.4 Cautions on Use 9.4.1 Cache Initialization Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to all valid bits for all entries (256 times), that is,those in the address range H'FFFFF000– H'FFFFF3FF. Writes to the address array or data array by the CPU, DMAC, or DTC are not possible while the cache is enabled. For reads, undefined values will be read out. 9.4.
CK Internal address Miss-hit Address Idle cycle CSn Idle cycle RD CS assert extension Idle cycle Data Figure 9.5 Cache Fill Timing in Case of Non-Consecutive Cache Miss from Normal Space (No Wait, No CS Assert Extension) CK Internal address Miss-hit Address CSn CS assert additional extension RD Data Figure 9.
CK Internal address Miss-hit Idle cycle Address ROW RAS COLUMN Idle cycle RAS assert extension CASxx Idle cycle Data Figure 9.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space (Normal Mode, TPC = 0, RCD = 0, No Wait) CS space access DRAM access DRAM access CK Internal address Address Miss-hit Miss-hit ROW COLUMN RAS Wait CS space COLUMN RAS assert extension CASxx Data Figure 9.
Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI without external circuitry. 10.1.
10.1.
10.1.3 Pin Configuration Table 10.1 shows the bus state controller pin configuration. Table 10.1 Pin Configuration Signal I/O Description A21–A0 O Address output (A21–A18 will become input ports with power-on reset) D31–D0 I/O 32-bit data bus. D15-D0 are address output and data I/O during address/data multiplex I/O. CS0– CS3 O Chip select RD O Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also output during DRAM access.
10.1.4 Register Configuration The BSC has eight registers. These registers are used to control wait states, bus width, and interfaces with memories like DRAM, ROM, and SRAM, as well as refresh control. The register configurations are listed in table 10.2. All registers are 16 bits. Do not access DRAM space before completing the memory interface settings. All BSC registers are all initialized by a power-on reset, but are not by a manual reset. Values are maintained in standby mode. Table 10.
10.1.5 Address Map Figure 10.2 shows the address format used by the SH7040 Series.
Table 10.
Table 10.
Bit: 15 14 13 12 11 10 9 8 — — MTU RWE — — — — IOE Initial value: 0 0 1 0 0 0 0 0 R/W: R R R/W R R R R R/W Bit: 7 6 5 4 3 2 1 0 A3LG A2LG A1LG A0LG A3SZ A2SZ A1SZ A0SZ 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: • Bits 15, 14, 12–9—Reserved: These bits always read as 0. The write value should always be 0. • Bit 13—MTU Read/Write Enable (MTURWE): When this bit is 1, MTU control register access is enabled.
• Bit 6—CS2 Space Long Size Specification (A2LG): Specifies the CS2 space bus size. Bit 6 (A2LG) Description 0 According to the A2SZ bit value (initial value) 1 Longword (32 bit) size • Bit 5—CS1 Space Long Size Specification (A1LG): Specifies the CS1 space bus size. Bit 5 (A1LG) Description 0 According to the A1SZ bit value (initial value) 1 Longword (32 bit) size • Bit 4—CS0 Space Long Size Specification (A0LG): Specifies the CS0 space bus size.
• Bit 1—CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size when A1LG = 0. Bit 1 (A1SZ) Description 0 Byte (8 bit) size 1 Word (16 bit) size (initial value) Note: This bit is ignored when A1LG = 1; CS1 space bus size becomes longword (32 bit). • Bit 0—CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size when A0LG = 0. Bit 0 (A0SZ) Description 0 Byte (8 bit) size 1 Word (16 bit) size (initial value) Note: A0SZ is effective only in on-chip ROM effective mode.
• Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access.
Bit 9 (IW01) Bit 8 (IW00) Description 0 0 No idle cycle after accessing CS0 space 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles (initial value) 1 • Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of the same CS space.
• Bits 3–0—CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. Refer to section 10.3.3, CS Assert Period Extension, for details.
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 W33 W32 W31 W30 W23 W22 W21 W20 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 W13 W12 W11 W10 W03 W02 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15–12—CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of waits for CS3 space access.
• Bits 7–4—CS1 Space Wait Specification (W13, W12, W11, W10): Specifies the number of waits for CS1 space access. Bit 7 (W13) Bit 6 (W12) Bit 5 (W11) Bit 4 (W10) Description 0 0 0 0 No wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 1 1 15 wait external wait input enabled (initial value) ⋅⋅⋅ 1 1 • Bits 3–0—CS0 Space Wait Specification (W03, W02, W01, W00): Specifies the number of waits for CS0 space access.
• Bits 15–6—Reserved: These bits always read as 0. The write value should always be 0. • Bits 5–4—DRAM Space DMA Single Address Mode Access Wait Specification (DDW1, DDW0): Specifies the number of waits for DRAM space access during DMA single address mode accesses. These bits are independent of the DWW and DWR bits of the DCR.
Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 TPC RCD TRAS1 TRAS0 DWW1 DWW0 DWR1 DWR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DIW — BE RASD SZ1 SZ0 AMX1 AMX0 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W • Bit 15—RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after RAS is negated before next assert. Bit 15 (TPC) Description 0 1.5 cycles (initial value) 1 2.
• Bits 11–10—DRAM Write Cycle Wait Count (DWW1–DWW0): Specifies the number of DRAM write cycle column address output cycles. Bit 11 (DWW1) Bit 10 (DWW0) Description 0 0 2-cycle (no wait) external wait disabled (initial value) 1 3-cycle (1 wait) external wait disabled 0 4-cycle (2 wait) external wait enabled 1 5-cycle (3 wait) external wait enabled 1 • Bits 9–8—DRAM Read Cycle Wait Count (DWR1–DWR0): Specifies the number of DRAM read cycle column address output cycles.
• Bits 3–2—DRAM Bus Width Specification (SZ1, SZ0): Specifies the DRAM space bus width. Bit 3 (SZ1) Bit 2 (SZ0) Description 0 0 Byte (8 bits) (initial value) 1 Word (16 bits) Don’t care Longword (32 bits) 1 • Bits 1–0—DRAM Address Multiplex (AMX1–AMX0): Specifies the DRAM address multiplex count. Bit 1 (AMX1) Bit 0 (AMX0) Description 0 0 9 bit (initial value) 1 10 bit 0 11 bit 1 12 bit 1 10.2.
• Bit 6—Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT and RTCOR match, is set/cleared under the following conditions: Bit 6 (CMF) Description 0 Clear condition: After RTCSR is read when CMF is 1, 0 is written in CMF. In some cases it will clear when DTC is activated by a compare match interrupt; refer to section 8, Data Transfer Controller (DTC), for details. (initial value) 1 Set condition: RTCNT = RTCOR.
• Bit 0—Refresh Mode (RMD): When the RFSH bit is 1, this bit selects normal refresh or selfrefresh. When the RFSH bit is 1, self-refresh mode is entered immediately after the RMD bit is set to 1. When RMD is cleared to 0, a CAS-before-RAS refresh is performed at the interval set in the refresh time constant register (RTCNT). When set for self-refresh, the SH7040 Series enters self-refresh mode immediately unless it is in the middle of a DRAM access.
10.2.8 Refresh Time Constant Register (RTCOR) RTCOR is a 16-bit read/write register that establishes the compare match period with RTCNT. The values of RTCOR and RTCNT are constantly compared. When the values correspond, the compare match flag of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the RTCSR is set to 1 and the RMD bit is 0, a refresh request signal is produced by this match. The refresh request signal is held until a refresh operation is performed.
10.3 Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 10.3.1 Basic Timing Figure 10.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are performed in 2 states. T1 T2 CK Address CSn RD Read Data WRx Write Data Figure 10.
10.3.2 Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings (figure 10.4). T1 TW T2 CK Address CSn RD Read Data WRx Write Data Figure 10.
When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 10.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when T w state shifts to T2 state. T1 TW TW TW0 T2 CK Address CSn RD Read Data WRx Write Data WAIT Figure 10.
10.3.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3–SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 10.6. Th and T f cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD and WRx signals are not.
10.4 DRAM Access 10.4.1 DRAM Direct Connection When address space A31–A24 = H'01 has been accessed, the corresponding space becomes a 16Mbyte DRAM space, and the DRAM interface function can be used to directly connect the SH7040 Series to DRAM. Row address and column address are always multiplexed for DRAM space. The amount of row address multiplexing can be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of the DCR. Table 10.
10.4.2 Basic Timing The SH7040 Series supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 10.7 shows the basic DRAM access timing. DRAM space access is controlled by RAS, CASx, and RDWR signals. The following signals are associated with transfer of these actual byte locations: CASHH (bits 31–24), CASHL (bits 23–16), CASH (bits 15–8), and CASL (bits 7–0).
10.4.3 Wait State Control Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1, DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and writes. The timing with waits inserted is shown in figures 10.8 through 10.11. External waits can be inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary space: at one cycle before the T c2 cycle clock rise. Wait cycles are extended by external waits.
Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw2 CK Address Row Column Data RAS Write CASx RDWR Data RAS Read CASx RDWR Figure 10.
Tp Tr Tc1 Tcw1 Tcw2 Tcw3 Tc2 CK Address Row Column Data RAS Write CASx RDWR Data RAS Read CASx RDWR Figure 10.
Tp Tr Tc1 Tcw1 Tcw2 Tcw0 Tc2 CK Address Row Column Data RAS Write CASx RDWR Data RAS Read CASx RDWR WAIT Figure 10.
10.4.4 Burst Operation High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be performed using high speed page mode. The timing is shown in figure 10.12. Wait cycles can be inserted during burst accesses by using the DCR. Tp Tr Tc1 Tc2 Tc1 Tc2 CK Address Row Column Column Data RAS Write CASx RDWR Data RAS Read CASx RDWR Figure 10.
DRAM access Tp Tr Tc1 Tc2 CS space access T1 T2 DRAM access Tp Tr Tc1 Tc2 CK Address Row Column CS space Row Column RAS CASx Data Figure 10.13 DRAM Access Normal Operation (RAS Up Mode) DRAM access Tp Tr Tc1 Tc2 CS space access T1 T2 DRAM access Tc1 Tc2 CK Address Row Column CS space RAS CASx Data Figure 10.
10.4.5 Refresh Timing The bus state controller is equipped with a function to control refreshes of DRAM. CAS-beforeRAS (CBR) refresh or self-refresh can be selected by setting the RTCSR’s RMD bit. CAS-before-RAS Refresh: For CBR refreshes, set the RCR’s RMD bit to 0 and the RFSH bit to 1. Also write the values in RTCNT and RTCOR necessary to fulfill the refresh interval prescribed for the DRAM being used.
Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the CAS signal and RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 10.16. Do not access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row addresses within the time prescribed for the particular DRAM.
10.5 Address/Data Multiplex I/O Space Access When the BCR1 register IOE bit is set to 1, the D15–D0 pins can be used for multiplexed address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data multiplexing can be directly connected to this LSI. Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0 and 16 bit when A14 = 1. 10.5.
10.5.2 Wait State Control Setting the WCR controls waits during address/data multiplex I/O space accesses. Software wait and external wait insertion timing is the same as during ordinary space accesses. The timing for one software wait + one external wait inserted is shown in figure 10.18. Ta1 Ta2 Ta3 Ta4 T1 TW TWo T2 CK Address CS3 AH Read RD Data Data input Address output WRx Write Data Address output Data output WAIT Figure 10.
10.5.3 CS Assertion Extension The timing diagram when setting CS assertion extension during address/data multiplex I/O space access is shown in figure 10.19. Ta1 Ta2 Ta3 Ta4 Th T1 T2 Tf Address CS3 AH Read RD Data Address output Data input WRxx Write Data Address output Data output Figure 10.19 Wait Timing in Address/Data Multiplex I/O Space when CS Assertion Extension is Set 10.
BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 10.20 shows an example of idles between cycles. In this example, 1 idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, 1 idle cycle is inserted.
10.6.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3–CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 10.21 shows an example.
to cause the external device to negate the BREQ and return the bus rights to the SH7040 Series. Please note that if the external device does not return the bus rights within the time prescribed for the DRAM refresh interval, this LSI will not be able to perform the refresh operation and the DRAM contents cannot be guaranteed. Figure 10.22 shows the bus right release procedure.
10.8 Memory Connection Examples Figures 10.23–10.31 show examples of the memory connections. As A21–A18 become input ports in power-on reset, they should be handled (e.g. pulled down) as necessary. 32k × 8 bits ROM SH704x CSn CE RD OE A0–A14 D0–D7 A0–A14 I/O0–I/O7 Figure 10.23 8-Bit Data Bus Width ROM Connection 256k × 16 bits ROM SH704x CSn CE RD OE A0 A1–A18 A0–A17 D0–D15 I/O0–I/O15 Figure 10.
256k × 16 bits ROM SH704x CSn CE RD OE A0 A1 A2–A19 A0–A17 D16–D31 I/O0–I/O15 D0–D15 CE OE A0–A17 I/O0–I/O15 Figure 10.25 32-Bit Data Bus Width ROM Connection 123k × 8 bits SRAM SH704x CSn CS RD OE A0–A16 WRL D0–D7 A0–A16 WE I/O0–I/O7 Figure 10.
SH704x 128k × 8 bits SRAM CSn RD A0 A1–A17 CS WRH D8–D15 WE OE A0–A16 I/O0–I/O7 WRL D0–D7 CS OE A0–A16 WE I/O0–I/O7 Figure 10.
128k × 8 bits SRAM SH704x CSn CS RD A0 A1 A2–A18 WRHH D24–D31 OE WRHL D16–D23 WRH D8–D15 WRL D0–D7 A0–A16 WE I/O0–I/O7 CS OE A0–A16 WE I/O0–I/O7 CS OE A0–A16 WE I/O0–I/O7 CS OE A0–A16 WE I/O0–I/O7 Figure 10.
512k × 8 bits DRAM SH704x RAS RDWR RAS WE OE A0–A9 CASL AD0–AD7 A0–A9 CAS I/O0–I/O7 Figure 10.29 8-Bit Data Bus Width DRAM Connection 256k × 16 bits DRAM SH704x RAS RAS RDWR WE OE A0 A1–A9 A0–A8 CASH UCAS CASL LCAS AD0–AD15 I/O0–I/O15 Figure 10.
256k × 16 bits DRAM SH704x RAS RAS RDWR WE A0 OE A1 A2–A10 A0–A8 CASHH UCAS CASHL AD16–AD31 LCAS I/O0–I/O15 CASH CASL AD0–AD15 RAS WE OE A0–A8 UCAS LCAS I/O0–I/O15 Figure 10.31 32-Bit Data Bus Width DRAM Connection 10.9 On-Chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 10.6. Table 10.
Cycles in which Bus is not Released (a) One bus cycle: The bus is never released during a single bus cycle. For example, in the case of a longword read (or write) in 8-bit normal space, the four memory accesses to the 8-bit normal space constitute a single bus cycle, and the bus is never released during this period. Assuming that one memory access requires two states, the bus is not released during an 8-state period. 8 bit 8 bit 8 bit 8 bit Cycles in which Bus is not Released Figure 10.
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Section 11 Direct Memory Access Controller (DMAC) 11.1 Overview The SH7040 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (transfer request acknowledge signal), external memories, memorymapped external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and UBC).
• • • • • Channel 3: Dual address mode only. Direct address transfer mode and indirect address transfer mode selectable. Reload function: Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. Transfer requests: There are three DMAC transfer activation requests, as indicated below. External request: From two DREQ pins. DREQ can be detected either by falling edge or by low level.
11.1.2 Block Diagram Figure 11.1 is a block diagram of the DMAC.
11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.
11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels Table 11.
Table 11.
Bit: 31 30 29 28 27 26 25 24 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 … … 2 1 0 … … R/W: Bit: Initial value: R/W: 11.2.2 — — — … … — — — R/W R/W R/W … … R/W R/W R/W DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer.
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). Specifying a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. The data for the upper 8 bits of a DMATCR is 0 when read. Always write 0. The initial value after power-on resets or in software standby mode is undefined.
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the operation and transmission of each channel is designated. They are initialized by a power-on reset and in software standby mode. There is no initializing with manual reset.
• Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for CHCR0, CHCR1, and CHCR3, and cannot be modified. Bit 19: RO Description 0 Does not reload source address (initial value) 1 Reloads source address • Bit 18—Request Check Level (RL): Selects whether to output DRAK notifying external device of DREQ received, with active high or active low.
• Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): These bits specify increment/decrement of the DMA transfer destination address. These bit specifications are ignored when transferring data from an external device to address space in single address mode.
• Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source. Bit 11: RS3 Bit 10: RS2 Bit 9: RS1 Bit 8: RS0 Description 0 0 0 0 External request, dual address mode (initial value) 0 0 0 1 Prohibited 0 0 1 0 External request, single address mode. External address space → external device. 0 0 1 1 External request, single address mode. External device → external address space.
• Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 5: TM Description 0 Cycle steal mode (initial value) 1 Burst mode • Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer.
• Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description 0 Operation of the corresponding channel disabled (initial value) 1 Operation of the corresponding channel enabled Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings). With an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled.
• Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of channels for execution when transfer requests are made for several channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description 0 0 CH0 > CH1 > CH2 > CH3 (initial value) 0 1 CH0 > CH2 > CH3 > CH1 1 0 CH2 > CH0 > CH1 > CH3 1 1 Round robin mode • Bits 7–3—Reserved bits: Data are 0 when read. The write value always be 0.
• Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of the CHCR is 1, or its DE bit is 0, transfer is disabled in the case of an NMI of the DMAOR or when AE = 1.
Figure 11.2 is a flowchart of this procedure.
11.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The request mode is selected in the RS3–RS0 bits of the DMA channel control registers 0–3 (CHCR0–CHCR3).
transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. The transfer request source need not be the data transfer source or transfer destination. However, when the transfer request is set by RxI (transfer request because SCI’s receive data is full), the transfer source must be the SCI’s receive data register (RDR).
11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order, either in a fixed mode or in round robin mode. These modes are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority levels among the channels remain fixed.
Transfer on channel 0 Initial priority setting Priority after transfer CH0 > CH1 > CH2 > CH3 Channel 0 is given the lowest priority. CH1 > CH2 > CH3 > CH0 Transfer on channel 1 Initial priority setting Priority after transfer CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 When channel 1 is given the lowest priority, the priority of channel 0, which was above channel 1, is also shifted simultaneously.
Figure 11.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The DMAC operates in the following manner under these circumstances: 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted first (channel 3 is on transfer standby). 3.
11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. It can operate in the single address mode, in which either the transfer source or destination is accessed using an acknowledge signal, or dual access mode, in which both the transfer source and destination addresses are output.
External address bus External data bus This LSI External memory DMAC External device with DACK DACK DREQ : Data flow Figure 11.5 Data Flow in Single Address Mode Two types of transfers are possible in the single address mode: (a) transfers between external devices with DACK and memory-mapped external devices, and (b) transfers between external devices with DACK and external memory. The only transfer requests for either of these is the external request (DREQ). Figure 11.
CK A21–A0 Address output to external memory space CSn Data that is output from the external device with DACK D15–D0 WRH WRL WR signal to external memory space DACK DACK signal to external devices with DACK (active low) a. External device with DACK to external memory space CK A21–A0 Address output to external memory space CSn Data that is output from external memory space D15–D0 RD RD signal to external memory space DACK DACK signal to external device with DACK (active low) b.
1st bus cycle DMAC SAR Data bus Address bus DAR Memory Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Data buffer Data bus Address bus DAR Memory Transfer source module Transfer destination module The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module.
CK A21–A0 Transfer source address Transfer destination address CSn D15–D0 RD WRH, WRL DACK Data read cycle (1st cycle) Note: Data write cycle (2nd cycle) Transfer between external memories with DACK are output during read cycle. Figure 11.
Indirect Address Transfer Mode: In this mode the memory address storing the data you actually want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first. This value is stored once in the DMAC. Next, the read value is output as the address, and the value stored at that address is again stored in the DMAC.
1st, 2nd bus cycles DMAC SAR3 Data bus Temporary buffer Address bus DAR3 Memory Transfer source module Transfer destination module Data buffer The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. When external connection data bus is 16 bits, two bus cycles are required.
CK A21–A0 Transfer source address (H) Transfer source address (L) NOP Indirect address Transfer destination address CSn D15–D0 Indirect address (H) Internal address bus Transfer source address *1 Internal data bus Indirect address (L) Transfer data Transfer data Indirect address NOP Transfer data Indirect address *2 DMAC indirect address buffer Transfer data Indirect address DMAC data buffer Transfer data RD WRH, WRL Address read cycle (1st) (2nd) NOP cycle Data read cycle Data
Figure 11.11 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write cycles are required.
11.3.7 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle steal and burst. Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master.
11.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.
11.3.9 Bus Mode and Channel Priority Order When a given channel is transferring in burst mode, and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. If the priority level setting is fixed mode (CH0 > CH1), channel 1 transfer is continued after transfer on channel 0 are completely ended, whether the channel 0 setting is cycle steal mode or burst mode.
DRAK is output once for the first DREQ sampling, irrespective of transfer mode or DREQ detection method. In burst mode, using edge detection, DREQ is sampled for the first cycle only, so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be ascertained, and this facilitates handshake operations of transfer requests with the DMAC.
Figure 11.
Figure 11.16 Cycle Steal, Dual Address, and Level Detection (Normal Operation) 249 CPU CPU CPU 2nd sampling DMAC(R) Note: With cycle-steal and dual address operation, sampling timing is the same whether DREQ detection is by level or by edge.
Figures 11.17 and 11.18 show cycle steal mode and single address mode. In this case, transfer begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode, the DACK signal is output during the DMAC transfer period.
DMAC CPU DMAC CPU DMAC CPU CPU DACK CPU Bus cycle DRAK DREQ CK Figure 11.
CPU DMAC CPU DMAC CPU CPU DACK CPU Bus cycle DRAK DREQ CK Figure 11.
Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with dual address and level detection is virtually the same as that of cycle steal mode. For example, DMAC transfer begins (figure 11.19), at the earliest, three cycles after the timing of the first sampling. The second sampling also begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued, DMAC transfer continues.
Figure 11.
DMAC(R) DMAC(R) DMAC(W) DMAC(W) DMAC(R) CPU CPU DACK CPU Bus cycle DRAK DREQ CK Figure 11.
Burst Mode, Single Address, and Level Detection: DREQ sampling timing in burst mode with single address and level detection is shown in figures 11.21 and 11.22. In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle, at the earliest, three cycles after timing of the first sampling. Data during this period is undefined, and the DACK signal is not output. Nor is the number of DMAC transfers counted. The actual DMAC transfer begins after one dummy bus cycle output.
Figure 11.
DMAC DMAC DMAC Dummy CPU CPU DACK CPU Bus cycle DRAK DREQ CK Figure 11.
Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 11.23, DMAC transfer begins, at the earliest, three cycles after the timing of the first sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the TCR. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first cycle only.
Figure 11.
Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 11.24, a dummy cycle is inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. Thereafter, DMAC transfer continues until the data transfer count set in the DMATCR has ended.
DMAC DMAC DMAC DMAC Dummy CPU CPU DACK CPU Bus cycle DRAK DREQ CK Figure 11.
11.3.11 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 11.25 illustrates this operation. Figure 11.26 is a timing chart for reload ON mode, with burst mode, autorequest, 16-bit transfer data size, SAR2 increment, and DAR2 fixed mode.
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set.
When the processing of a one unit transfer is complete. In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and TCR values are updated. In the same manner, the transfer is not halted in dual address mode indirect address transfers until after the final write processing has ended.
11.4.2 Example of DMA Transfer between External RAM and External Device with DACK In this example, an external request, serial address mode transfer with external memory as the transfer source and an external device with DACK as the transfer destination is executed using DMAC channel 1. Table 11.8 indicates the transfer conditions and the setting values of each of the registers. Table 11.
Table 11.
Table 11.10 DMAC Internal Status Item Address Reload On Address Reload Off SAR H'FFFF83F0 H'FFFF83F4 DAR H'FFFFF004 H'FFFFF004 DMATCR H'0000007C H'0000007C Bus rights Released Maintained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1.
Table 11.
Table 11.12 DMAC Internal Status Item Address Reload On Address Reload Off SAR H'FFFF8408 H'FFFF840C DAR H'FFFFF004 H'FFFFF004 DMATCR H'0000007C H'0000007C Bus rights Released Maintained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1.
Table 11.
11.5 Cautions on Use 1. Other than the DMA operation register (DMAOR) accessing in word (16-bit) units, access all registers in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (set the DE bit to 0 before doing rewrites with a CHCR byte address). 3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is not operating. 4.
Section 12 Multifunction Timer Pulse Unit (MTU) 12.1 Overview The SuperH microprocessor has an on-chip 16-bit multifunction timer pulse unit (MTU) with five channels of 16-bit timers. 12.1.1 Features • Can process a maximum of sixteen different pulse outputs and inputs. • Has sixteen timer general registers (TGR): four each for channels 0, 3, and 4, and two each for channels 1 and 2 that can be set to function independently as output compare or input capture.
• • • • Complementary PWM mode: By combining channels 3 and 4, a triangle wave comparator type six-phase PWM output is possible with non-overlapping times. High speed access via internal 16-bit bus Twenty-three interrupt sources Channels 0, 3, and 4 have four compare-match/input capture interrupts and one overflow interrupt which can be requested independently.
Table 12.1 summarizes the MTU functions. Table 12.
Table 12.
TCNT TGRA TGRB TGRC TGRD TCNT TGRA TGRB TGRC TGRD BUS I/F TCNTS TCDR TCBR TDDR TCNT TGRA TGRB Module data bus TSTR TSYR Control logic TOER TOCR TGCR Channel 3 TCR TMDR TIORH TIORL TIER TSR Channel 4 TCR TMDR TIOR TIORL TIER TSR TCNT TGRA TGRB Channel 2: TIOC2A TIOC2B TCNT TGRA TGRB TGRC TGRD Channel 1: TIOC1A TIOC1B Channel 2 TCR TMDR TIOR TIER TSR (I/O pins) Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channels 0–2 control logic External clock: TCLKA TCLKB TCLKC TCLKD Channel 1 TCR TMDR TIOR TIER
12.1.3 Pin Configuration Table 12.2 summarizes the MTU pins. Table 12.
Table 12.
12.1.4 Register Configuration Table 12.3 summarizes the MTU register configuration. Table 12.
Table 12.
Table 12.
12.2 MTU Register Descriptions 12.2.1 Timer Control Register (TCR) The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The MTU has five TCR registers, one for each of the channels 0 to 4. TCR is initialized to H'00 by a power-on reset or the standby mode. Manual reset does not initialize TCR.
Channels 0, 3, 4: Bit 7: Bit 6: CCLR2 CCLR1 Bit 5: CCLR0 Description 0 0 TCNT clear disabled (initial value) 1 TCNT is cleared by TGRA compare-match or input capture 0 TCNT is cleared by TGRB compare-match or input capture 1 Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync.
Bit 4: Bit 3: CKEG1 CKEG0 Description 0 1 0 Count on rising edges (initial value) 1 Count on falling edges X Count on both rising and falling edges Notes: 1. X: 0 or 1, don’t care. 2. Internal clock edge selection is effective when the input clock is φ/4 or slower. When ø/1 or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation complies with the initial value (count on rising edges).
Channel 1: Bit 2: Bit 1: TPSC2 TPSC1 Bit 0: TPSC0 Description 0 0 Internal clock: count with φ/1 (initial value) 1 Internal clock: count with φ/4 0 Internal clock: count with φ/16 1 Internal clock: count with φ/64 0 External clock: count with the TCLKA pin input 1 External clock: count with the TCLKB pin input 0 Internal clock: count with φ/256 1 Count with the TCNT2 overflow/underflow 0 1 1 0 1 Note: These settings are ineffective when channel 1 is in phase counting mode.
Channel 3: Bit 2: Bit 1: TPSC2 TPSC1 Bit 0: TPSC0 Description 0 0 Internal clock: count with φ/1 (initial value) 1 Internal clock: count with φ/4 0 Internal clock: count with φ/16 1 Internal clock: count with φ/64 0 Internal clock: count with φ/256 1 Internal clock: count with φ/1024 0 External clock: count with the TCLKA pin input 1 External clock: count with the TCLKB pin input Bit 2: Bit 1: TPSC2 TPSC1 Bit 0: TPSC0 Description 0 0 Internal clock: count with φ/1 (initial value) 1
12.2.2 Timer Mode Register (TMDR) The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has five TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset or the standby mode. Manual reset does not initialize TMDR.
• Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal operation, or buffer operation in combination with the TGRC register. When using TGRC as a buffer register, no TGRC register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0, and cannot be modified.
12.2.3 Timer I/O Control Register (TIOR) The TIOR is a register that controls the TGR. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset or the standby mode. Manual reset does not initialize TIOR.
Channel 0 (TIOR0H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR0B register function.
• Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR0A register function.
Channel 0 (TIOR0L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR0D register function.
• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR0C register function.
Channel 1 (TIOR1 Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR1B register function.
• Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR1A register function.
Channel 2 (TIOR2 Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR2B register function.
• Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR2A register function.
Channel 3 (TIOR3H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR3B register function.
• Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR3A register function.
Channel 3 (TIOR3L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR4D register function.
• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR4C register function.
Channel 4 (TIOR4H Register): • Bits 7–4—I/O Control B3–B0 (IOB3–IOB0): These bits set the TGR4B register function.
• Bits 3–0—I/O Control A3–A0 (IOA3–IOA0): These bits set the TGR4A register function.
Channel 4 (TIOR4L Register): • Bits 7–4—I/O Control D3–D0 (IOD3–IOD0): These bits set the TGR4D register function.
• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR4C register function.
Channels 1, 2: TIER1, TIER2: Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA 0 1 0 0 0 0 0 0 R/W R R/W R/W R R R/W R/W 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA 0 1 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W Channels 3, 4: TIER3, TIER4: Bit: Initial value: R/W: • Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input c
• Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0, 3, 4 TSR register is set to 1. This bit is reserved for channels 1 and 2. It always reads as 1. The write value should always be 1.
12.2.5 Timer Status Register (TSR) The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has five TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset or by standby mode. This register is not initialized by a manual reset.
• Bit 5—Underflow Flag (TCFU): This status flag indicates the occurrence of a channel 1, 2 TCNT counter underflow. This bit is reserved in channels 0, 3, and 4. This bit always reads as 0. The write value should always be 0. Bit 5: TCFU Description 0 Clear condition: With TCFU=1, a 0 write to TCFU after reading it (initial value) 1 Set condition: When the TCNT value underflows (H'0000 → H'FFFF) • Bit 4—Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter overflow.
• Bit 2—Input Capture/Output Compare Flag C (TGFC): This status flag indicates the occurrence of a channel 0, 3, or 4 TGRC register input capture or compare-match. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
12.2.6 Timer Counters (TCNT) The timer counters (TCNT) are 16-bit counters, with one for each channel, for a total of five. The TCNT are initialized to H'0000 by a power-on reset and when in standby mode. Manual reset does not initialize TCNT. Accessing the TCNT counters in 8-bit units is prohibited. Always access in 16-bit units.
12.2.7 Timer General Register (TGR) Each timer general register (TGR) is a 16-bit register that can function as either an output compare register or an input capture register. There are a total of sixteen TGR, four each for channels 0, 3, and 4, and two each for channels 1 and 2. The TGRC and TGRD of channels 0, 3, and 4 can be set to operate as buffer registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB with TGRD.
Counter Start Channel CST4 Channel 4 (TCNT4) CST3 Channel 3 (TCNT3) CST2 Channel 2 (TCNT2) CST1 Channel 1 (TCNT1) CST0 Channel 0 (TCNT0) Bit n: CSTn Description 0 TCNTn count is halted (initial value) 1 TCNTn counts Note: n = 4 to 0. However, CST4 is bit 7, CST3 is bit 6. If 0 is written to the CST bit during operation with the TIOC pin in output status, the counter stops, but the TIOC pin output compare output level is maintained.
Counter Start Channel SYNC4 Channel 4 (TCNT4) SYNC3 Channel 3 (TCNT3) SYNC2 Channel 2 (TCNT2) SYNC1 Channel 1 (TCNT1) SYNC0 Channel 0 (TCNT0) Bit n: SYNCn Description 0 Timer counter (TCNTn) independent operation (initial value) (TCNTn preset/clear unrelated to other channels) Timer counter synchronous operation* 1 1 TCNTn synchronous preset/ synchronous clear* 2 possible Notes: n = 4 to 0. However, SYNC4 is bit 7, SYNC3 is bit 6.
• Bit 5—Master Enable TIOC4D (OE4D): Enables or disables the TIOC4D pin MTU output. Bit 5: OE4D Description 0 Disable TIOC4D pin MTU output (initial value) 1 Enable TIOC4D pin MTU output • Bit 4—Master Enable TIOC4C (OE4C): Enables or disables the TIOC4C pin MTU output. Bit 4: OE4C Description 0 Disable TIOC4C pin MTU output (initial value) 1 Enable TIOC4C pin MTU output • Bit 3—Master Enable TIOC3D (OE3D): Enables or disables the TIOC3D pin MTU output.
12.2.11 Timer Output Control Register (TOCR) The timer output control register (TOCR) enables/disables PWM synchronized toggle output in complementary PWM mode and reset sync PWM mode, and controls output level inversion of PWM output. The TOCR is initialized to H'00 by a power-on reset or in the standby mode. Manual reset does not initialize TOCR. These register settings are ineffective for anything other than complementary PWM mode/reset-synchronized PWM mode.
Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT3 and TCNT4 values TGR3A TCNT4 TCNT3 TGR4A TDDR H'0000 Positive phase output Time Compare match output (up count) Initial output Initial output Reverse phase output Compare match output (down count) Active level Compare match output (down count) Compare match output (up count) Active level Active level Figure 12.2 Complementary PWM Mode Output Level Example 12.2.
• Bit 6—Brushless DC Motor (BDC): Selects gate signal output/chopping output function for brushless DC motor control. Bit 6: BDC Description 0 Ordinary output (initial value) 1 Gate signal/chopping output for brushless DC motor • Bit 5—Reverse Phase Output (N): Selects whether to output gate signals directly to the reverse phase pin (TIOC3D, TIOC4C, and TIOC4D) output, or to output by chopping the gate signal and the complementary PWM/reset-synchronized PWM output.
• Bits 2–0—Output Phase Switch 2–0 (WF, VF, UF): These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2–0 is a substitute for external input.
12.2.14 Timer Dead Time Data Register (TDDR) The timer dead time data register (TDDR) is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT3 and TCNT4 counter offset values. In complementary PWM mode, when the TCNT3 and TCNT4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT3 counter and the count operation starts. The TDDR register is initialized to H'FFFF by a power-on reset or in standby mode. Manual reset does not initialize TDDR.
12.2.16 Timer Period Buffer Register (TCBR) The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing established in the TMDR register. The TCBR register is initialized to H'FFFF by a power-on reset or in standby mode. Manual reset does not initialize TCBR. Accessing the TCBR in 8-bit units is prohibited.
12.3.2 8-Bit Registers All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 12.4 ,12.5, and 12.6). Internal data bus Upper 8 bits Module data bus Bus interface Bus master Lower 8 bits TCR Figure 12.
12.4 Operation 12.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers (TGR) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset.
Complementary PWM Mode: Three-phase complementary positive and negative PWM waveforms whose positive and negative phases do not overlap can be obtained using channels 3 and 4. When set for complementary PWM mode, TGR3A, TGR3B, TGR4A, and TGR4B become output compare registers. The TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins also automatically become PWM output pins while TCNT3 and TCNT4 become up/down counters. 12.4.
Counting mode selection Select counter clock 1 Free-running counter Periodic counter Select counter clear source 2 Select output compare register 3 Set period 4 Start counting 5 Periodic counter Start counting 5 Free-running counter Figure 12.7 Procedure for Selecting the Counting Operation Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves them all in the free-running mode.
Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel’s TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period setting to output compare register and select counter clear upon compare-match using the CCLR2–CCLR0 bits of the timer control register (TCR). After these settings, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1.
Output selection Select waveform output mode 1 Select output timing 2 Start counting 3 Figure 12.10 Procedure for Selecting Compare Match Waveform Output Operation Waveform Output Operation (0 Output/1 Output): Figure 12.11 shows 0 output/1 output. In the example, TCNT is a free-running counter, 1 is output upon compare-match A and 0 is output upon compare-match B. When the pin level matches the set level, the pin level does not change.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time TIOCA Toggle output TIOCB Toggle output Figure 12.12 Example of Toggle Output Input Capture Function: In the input capture mode, the TCNT value is transferred into the TGR register when the input edge is detected at the input capture/output compare pin (TIOC). Detection can take place on the rising edge, falling edge, or both edges.
Input Capture Operation: Figure 12.14 shows input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to clear at the input capture of the TGRB register. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 12.14 Input Capture Operation 12.4.
Procedure for Selecting the Synchronizing Mode (Figure 12.15): 1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with output compare/input capture using bits CCLR2–CCLR0 in the TCR. 4.
Synchronized Operation: Figure 12.16 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A, TIOC1A, and TIOC2A pins. See section 12.4.
12.4.4 Buffer Operation Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer registers. Table 12.5 shows the register combinations for buffer operation. Table 12.5 Register Combinations Channel General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D TGR3A TGR3C TGR3B TGR3D TGR4A TGR4C TGR4B TGR4D 3 4 The buffer operation differs, depending on whether the TGR has been set as an input capture register or an output compare register.
Procedure for Setting Buffer Mode (Figure 12.19): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode. 3. Set the CST bit in the TSTR to 1 to start the count operation. Buffer mode Select TGR function 1 Select buffer mode 2 Start counting 3 Buffer mode Figure 12.
TCNT value TGR0B H'0520 H'0450 H'0200 TGR0A H'0000 Time H'0200 TGR0C Transfer TGR0A H'0450 H'0200 H'0520 H'0450 TIOC0A Figure 12.20 Buffer Operation Example (Output Compare Register) Buffer Operation Examples—when TGR Is an Input Capture Register: Figure 12.21 shows an example of TGRA set as an input capture register with the TGRA and TGRB registers set for buffer operation.
12.4.5 Cascade Connection Mode Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2–TPSC0 bits of the TCR register to set the channel 1 counter clock to count by TCNT2 counter overflow/underflow. Note: When channel 1 is set to phase counting mode, the counter clock settings become ineffective. Table 12.6 shows the cascade connection combinations. Table 12.
Cascade Connection Operation Examples—Phase Counting Mode: Figure 12.23 shows an example of operation when the TCNT1 counter is set to count on TCNT2 overflow/underflow and channel 2 is set to phase counting mode. The TCNT1 counter increments with a TCNT2 counter overflow and decrements with a TCNT2 underflow. TCLKC TCLKD TCNT2 FFFD FFFE FFFF 0000 TCNT1 0000 0001 0002 0001 0001 0000 FFFF 0000 Figure 12.23 Cascade Connection Operation Example (Phase Counting Mode) 12.4.
Table 12.7 lists the combinations of PWM output pins and registers. Table 12.
PWM mode Select counter clock 1 Select counter clear source 2 Select waveform output level 3 Set TGR 4 Select PWM mode 5 Start counting 6 PWM mode Figure 12.24 Procedure for Selecting the PWM Mode PWM Mode Operation Examples—PWM Mode 1 (Figure 12.25): A TGRA register comparematch is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value are both 0, and the TGRB register output compare output value is a 1.
PWM Mode Operation Examples—PWM Mode 2 (Figure 12.26): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare output value is 1, and a 5-phase PWM waveform is output. In this example, the value established in the TGR1B register becomes the period and the value established in the other TGR register becomes the duty cycle.
100% Duty Cycle: Figure 12.28 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter.
The TSR register TCFD bit is a count direction flag. Read the TCFD flag to confirm whether the TCNT is incrementing or decrementing. Table 12.8 shows the correspondence between channels and external clock pins. Table 12.8 Phase Counting Mode Clock Input Pins Channel A Phase Input Pin B Phase Input Pin 1 TCLKA TCLKB 2 TCLKC TCLKD Procedure for Selecting the Phase Counting Mode (Figure 12.29): 1. Set the MD3–MD0 bits of the timer mode register (TMDR) to select the phase counting mode. 2.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Figure 12.30 Phase Counting Mode 1 Operation Table 12.
Phase Count Mode 2: Figure 12.31 shows an example of phase counting mode 2 operation. Table 12.10 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement Time Figure 12.31 Phase Counting Mode 2 Operation Table 12.
Phase Count Mode 3: Figure 12.32 shows an example of phase counting mode 3 operation. Table 12.11 lists the up counting and down counting conditions for the TCNT. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Figure 12.32 Phase Counting Mode 3 Operation Table 12.
Phase Count Mode 4: Figure 12.33 shows an example of phase counting mode 4 operation. Table 12.12 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement Time Figure 12.33 Phase Counting Mode 4 Operation Table 12.
input clock is used as the TGR0B register input capture source, and a pulse width of four times the 2-phase encoder pulse is detected. The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0 TGR0A and TGR0C register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored.
12.4.8 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins become PWM output pins and TCNT3 becomes an upcounter. Table 12.13 shows the PWM output pins used. Table 12.14 shows the settings of the registers. Table 12.
4. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 5. Reset TCNT3 and TCNT4 to H'0000. 6. TGR3A is the period register. Set the waveform period value in TGR3A. Set the transition times of the PWM output waveforms in TGR3B, TGR4A, and TGR4B. Set times within the compare-match range of TCNT3. X ≤ TGR3A (X: set value).
Reset-synchronized PWM mode Stop counting 1 Select counter clock 2 Select counter clear source 3 Brushless DC motor control setting 4 Set TCNT 5 Set TGR 6 PWM cycle output enabling, PWM output level setting 7 Set reset-synchronized PWM mode 8 Enable PWM output 9 Start count operation 10 Reset-synchronized PWM mode Figure 12.
Reset-Synchronized PWM Mode Operation: Figure 12.36 shows an example of operation in the reset-synchronized PWM mode. TCNT3 and TCNT4 operate as upcounters. The counter is cleared when a TCNT3 and TGR3A compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGR3B, TGR4A, TGR4B compare-match, and upon counter clears. TCNT3 and TCNT4 values TGR3A TGR3B TGR4A TGR4B H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 12.
12.4.9 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins become PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT3 and TCNT4 function as increment/decrement counters. Table 12.15 shows the PWM output pins used. Table 12.16 shows the settings of the registers.
Table 12.
TGR3A TCDR Comparator TCNT3 Match signal TCNTS TCNT4 TGR3D TGR4C TGR4B Temp 3 Match signal TGR4A Temp 2 TGR3B Temp 1 Comparator PWM cycle output Output protection circuit TCBR Output controller TCNT4 underflow interrupt TGR3A comparematch interrupt ;; ÀÀ @@ À @ ; ;; ÀÀ @@ ; ÀÀ @@ ;; ; ;; ÀÀ @@ ; @; À ; @;; À @@ ÀÀ @; À ; @;; À @@ ÀÀ À @ ; TDDR TGR3C PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0
Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 12.38. 1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT3 and TCNT4 are stopped. 2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2–TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR).
Complementary PWM mode Stop count operation 1 Counter clock, counter clear source selection 2 Brushless DC motor control setting 3 TCNT setting 4 Inter-channel cycle setting 5 TGR setting 6 Dead time, carrier cycle setting 7 PWM cycle output enabling, PWM output level setting 8 Complementary PWM mode setting 9 Enable waveform output 10 Start count operation 11 Figure 12.
Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM mode, and figure 12.40 shows an example of complementary PWM mode operation. • Counter operation In complementary PWM mode, three counters—TCNT3, TCNT4, and TCNTS—perform up/down-count operations. TCNT3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0.
• Register operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGR3B, TGR4A, and TGR4B. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output.
Transfer from temporary register to compare register Tb2 Transfer from temporary register to compare register Ta Tb1 Ta Tb2 Ta TGR3A TCNTS TCDR TCNT3 TGR4A TCNT4 TGR4C TDDR H'0000 Buffer register TGR4C H'6400 H'0080 Temporary register TEMP2 H'6400 H'0080 Compare register TGR4A H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 12.
• Initialization In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3–MD0 in the timer mode register (TMDR), the following initial register values must be set. TGR3C operates as the buffer register for TGR3A, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle.
• PWM cycle setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGR3A, in which the TCNT3 upper limit value is set, and TCDR, in which the TCNT4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGR3A set value = TCDR set value + TDDR set value The TGR3A and TCDR settings are made by setting the values in buffer registers TGR3C and TCBR.
• Register data updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register.
Figure 12.
• Initial output in complementary PWM mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT4 exceeds the value set in the dead time register (TDDR). Figure 12.43 shows an example of the initial output in complementary PWM mode.
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT3, 4 value TCNT3 TCNT4 TDDR TGR4A Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT3, 4 count start (TSTR setting) Figure 12.
• Complementary PWM mode PWM output generation method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register.
T2 period T1 period T1 period TGR3A c d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.45 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGR3A c d TCDR a b a b TDDR H'0000 Positive phase Negative phase Figure 12.
T1 period T2 period T1 period TGR3A TCDR a b TDDR c a' d b' H'0000 Positive phase Negative phase Figure 12.47 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period c TGR3A T1 period d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.
T1 period T2 period T1 period TGR3A TCDR a b a b TDDR H'0000 c d Positive phase Negative phase Figure 12.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period c TGR3A T1 period d TCDR a b TDDR H'0000 Positive phase Negative phase Figure 12.
T1 period T2 period T1 period TGR3A TCDR a b TDDR H'0000 c b' d a' Positive phase Negative phase Figure 12.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGR3A T2 period c ad T1 period b TCDR TDDR H'0000 Positive phase Negative phase Figure 12.
• Complementary PWM mode 0% and 100% duty output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 12.48 to 12.52 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGR3A. The waveform in this case has a positive phase with a 100% off-state.
• Counter clearing by another channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2–CCLR0 in the timer control register (TCR), it is possible to have TCNT3, TCNT4, and TCNTS cleared by another channel. Figure 12.54 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal.
• Example of AC synchronous motor (brushless DC motor) drive waveform output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 12.55 to 12.58 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0.
External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.56 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 12.
TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.58 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) • A/D conversion start request setting In complementary PWM mode, an A/D conversion start request can be issued using a TGR3A compare-match or a compare-match on a channel other than channels 3 and 4.
Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. • Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus control register 1 (BCR1).
12.5 Interrupts 12.5.1 Interrupt Sources and Priority Ranking The MTU has three interrupt sources: TGR register compare-match/input captures, TCNT counter overflows and TCNT counter underflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled.
Table 12.
12.5.2 DTC/DMAC Activation DTC Activation: The TGR register input capture/compare-match interrupt of any channel can be used as a source to activate the on-chip data transfer controller (DTC). For details, refer to section 8, Data Transfer Controller (DTC). The MTU has 17 input capture/compare-match interrupts that can be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, and five for channel 4.
12.6 Operation Timing 12.6.1 Input/Output Timing TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 12.59. Count timing with external clock operation (normal mode) is shown in figure 12.60, and figure 12.61 shows count timing with external clock operation (phase counting mode). φ Internal clock Falling edge Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 12.
φ External clock Falling edge Rising edge Falling edge TCNT input clock N–1 TCNT N N+1 Figure 12.61 TCNT Count Timing during External Clock Operation (Phase Counting Mode) Output Compare Output Timing: The compare-match signal is generated at the final state of TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR or TOCR is output to the output compare output pin (TIOC pin).
φ TCNT input clock TCNT N TGR N N+1 Comparematch signal TIOC pin Figure 12.63 Output Compare Output Timing (Complementary PWM Mode/Reset Sync PWM Mode) Input Capture Signal Timing: Figure 12.64 illustrates input capture timing. φ Input capture input Rising edge Falling edge Input capture signal TCNT TGR N N+1 N+2 N Figure 12.
Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 12.65. Figure 12.66 shows the timing for counter clearing due to input capture. φ Comparematch signal Counter clear signal TCNT N TGR N H'0000 Figure 12.65 Counter Clearing Timing (Compare-Match) φ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 12.
Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 12.67. Figure 12.68 shows input capture buffer operation timing. φ n n+1 TGRA, TGRB n N TGRC, TGRD N TCNT Comparematch signal Comparematch buffer signal Figure 12.67 Buffer Operation Timing (Compare-Match) φ Input capture signal Input capture signal buffer TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 12.
12.6.2 Interrupt Signal Timing Setting TGF Flag Timing during Compare-Match: Figure 12.69 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Comparematch signal TGF flag TGI interrupt Figure 12.69 TGI Interrupt Timing (Compare Match) Setting TGF Flag Timing during Input Capture: Figure 12.
φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 12.70 TGI Interrupt Timing (Input Capture) Setting Timing for Overflow Flag (TCFV)/Underflow Flag (TCFU): Figure 12.71 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing. Figure 12.72 shows timing for the TCFU flag of the timer status register (TSR) due to underflow, as well as TCIU interrupt request signal timing. Figure 12.
φ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 12.72 TCIU Interrupt Setting Timing φ TCNT input clock TCNT (underflow) H'0001 H'0000 H'0001 Underflow signal TCFV flag TCIV interrupt Figure 12.
Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. For DTC/DMA controller activation, clearing can also be done automatically. Figure 12.74 shows the timing for status flag clearing by the CPU. Figure 12.75 shows timing for clearing due to the DTC/DMA controller. TSR write cycle T1 T2 φ Address TSR address Write signal Status flag Interrupt request signal Figure 12.
12.7 Notes and Precautions This section describes contention and other matters requiring special attention during MTU operations. 12.7.1 Input Clock Limitations The input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states or greater for both edges. Normal operation cannot be guaranteed with lesser pulse widths. In phase counting mode, the phase difference between the two input clocks and the overlap must be 1.
12.7.3 Contention between TCNT Write and Clear If a counter clear signal is issued in the T 2 state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 12.77). TCNT write cycle T1 T2 φ Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 12.
12.7.4 Contention between TCNT Write and Increment If a count-up signal is issued in the T2 state during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure 12.78). TCNT write cycle T1 T2 φ Address TCNT address Write signal TCNT input clock TCNT N M TCNT write data Figure 12.
12.7.5 Contention between Buffer Register Write and Compare Match If a compare-match occurs in the T2 state of the TGR write cycle, data is transferred by the buffer operation from the buffer register to the TGR. Data to be transferred differs depending on channels 0 and 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write (figures 12.79 and 12.80).
TGR write cycle T1 T2 φ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register TGR Buffer register write data N M N Figure 12.
12.7.6 Contention between TGR Read and Input Capture If an input capture signal is issued in the T1 state of the TGR read cycle, the read data is that after input capture transfer (figure 12.81). TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR Internal data bus X M M Figure 12.
12.7.7 Contention between TGR Write and Input Capture If an input capture signal is issued in the T2 state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 12.82). TGR write cycle T1 T2 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 12.
12.7.8 Contention between Buffer Register Write and Input Capture If an input capture signal is issued in the T2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 12.83). Buffer register write cycle T1 T2 φ Address Buffer register address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 12.
12.7.9 Contention between TGR Write and Compare Match If a compare-match occurs in the T2 state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 12.84). TGR write cycle T1 T2 φ Address TGR address Write signal Compare match signal TCNT N N+1 TGR N M TGR write data Figure 12.84 TGR Write and Compare Match Contention 12.7.
TCNT write cycle T1 T1 φ Address TCNT2 address Write signal TCNT2 H'FFFE H'FFFF N N+1 TCNT2 write data TGR2A–B H'FFFF Ch2 comparematch signal A/B Disabled TCNT1 input clock TCNT1 M TGR1A M Ch1 comparematch signal A TGR1B N M Ch1 inputcapture signal B TCNT0 P TGR0A–D Q P Ch0 input capture signal A–D Figure 12.
12.7.11 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT3 and TCNT4 in complementary PWM mode, TCNT3 has the timer dead time register (TDDR) value, and TCNT4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state (figure 12.86). When counting begins in another operating mode, be sure that TCNT3 and TCNT4 are set to the initial values.
12.7.13 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR3. For example, if the BFA bit of TMDR3 is set to 1, TGR3C functions as the buffer register for TGR3A.
TGR3A TCNT3 Point a TGR3C Buffer transfer with compare match A3 TGR3A, TGR3C TGR3B, TGR4A, TGR4B TGR3D, TGR4C, TGR4D Point b TGR3B, TGR3D, TGR4A, TGR4C, TGR4B, TGR4D H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGF3C TGF3D TGF4C TGF4D Not set Not set Set Set Figure 12.
When setting the buffer operation in the reset synchronous PWM mode, it is not necessary to set the timer interrupt enable register’s (TIER4) TGIEC and TGIED bits to 0, to prohibit interrupt output. Figure 12.88 shows an example of operations for TGR3, TGR4, TIOC3, and TIOC4, with TMDR3’s BFA and BFB bits set to 1, and TMDR4’s BFA and BFB bits set to 0.
When TCNT3 and TCNT4 count up to H'FFFF, a compare-match occurs with TGR3A, and TCNT3 and TCNT4 are both cleared. At this point, TSR3’s TCFV bit is not set, but the TCFV bit of TSR4 is set. This can be avoided by sync setting for channel 3 and channel 4. Set the SYNC3 and SYNC4 bits of the timer sync register (TSYR) to 1, compare-match with TGR3A by TCR3 for the counter clear source, and sync clear with TCR4. This gives the sync setting for channels 3 and 4. Figure 12.
Counter clear by compare match 3A TGR3A (H'FFFF) TCNT3=TCNT4 H'0000 TCF3V Not set TCF4V Not set Figure. 12.
12.7.15 Notes on Compare Match Flags in Complementary PWM Mode In complementary PWM mode, buffer register compare-match flags can be set only for compare with three counters (TCNT3, TCNT4, and TCNTS). Note that when the buffer register set value is dead time (Td), 2Td, TGR3A – Td, or TGR3A – 2Td, the buffer register compare-match flag may not be set. Figure 12.91 gives a description when TGR3B is the specified duty setting register, TGR3D the buffer register with TGR3A – Td as the buffer register set value.
• A mask operation For A mask, the above operation is modified as follows: In complementary PWM mode, buffer register compare-match flags can be set only for compare with three counters (TCNT3, TCNT4, and TCNTS). Special properties of compare match flag disappear and compare match flags of buffer registers are set to all set values of buffer registers. Figure 12.92 shows an example when setting the duty setting register to TGR3B, buffer register to TGR3D and Buffer register to TGR3A-Td.
12.7.16 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.93 shows the operation timing when a TGR compare-match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF flag Disabled TCFV flag Figure 12.
12.7.17 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 12.94 shows the operation timing in this case. TCNT write cycle T1 T2 φ Address TCNT address Write signal TCNT input clock TCNT H'FFFF N TCNT write data Disabled TCFV flag Figure 12.
12.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct.
Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM output when setting buffer operation only for the TGRD register in PWM mode. When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and TGRD registers as buffer registers. 12.7.
Figure 12.95 shows an example of the duration while the temporary register is executing comparisons. initial TB, TA, and TB indicate the duration of the temporary register comparison. initial TB TGR3A TCDR TDDR TA TB TA TB TCNT3 TCNT4 H'0000 Figure. 12.95 Temporary Register Comparison Execution Time 12.8 MTU Output Pin Initialization 12.8.1 Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes.
12.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc.
• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. • In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.
(1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.96 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
(2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.97 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
(3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 12.98 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
(4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.99 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after resetting.
(5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.100 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
(6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.101 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting.
(7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 12.102 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
(8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 12.103 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
(9) Operation when Rrror Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 12.104 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.105 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after resetting.
(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.106 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.107 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting.
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 12.108 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 12.109 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
(15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 12.110 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.111 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after resetting.
(17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.112 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.113 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
(19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 12.114 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 12.115 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
(21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.116 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.117 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
(23a) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.118 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
(23b) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.119 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.120 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode.
(25) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 12.121 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal mode after re-setting.
(26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 12.122 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting.
(27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 12.123 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting.
(28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 12.124 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re-setting.
12.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0–POE3 pin input, depending on the output status of the high-current pins (PE09/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C/DACK0/AH, PE15/TIOC4D/DACK1/IRQOUT). It can also simultaneously generate interrupt requests.
12.9.2 Block Diagram The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 12.125.
12.9.3 Pin Configuration Table 12.18 shows the POE pins. Table 12.18 Pin Configuration Name Abbreviation I/O Description Port output enable input pins POE0–POE3 Input Input request signals to make highcurrent pins high-impedance state Table 12.19 shows output-level comparisons with pin combinations. Table 12.
12.10 POE Register Descriptions 12.10.1 Input Level Control/Status Register (ICSR) The input level control/status register (ICSR) is a 16-bit read/write register that selects the POE0– POE3 pin input modes, controls the enable/prohibit of interrupts, and indicates status. If any of the POE3F–POE0F bits are set to 1, the high current pins become high impedance state.
• Bit 13—POE1 Flag (POE1F): This flag indicates that a high impedance request has been input to the POE1 pin. Bit 13: POE1F Description 0 Clear condition: By writing 0 to POE1F after reading a POE1F = 1 (initial value) 1 Set condition: When the input set by ICSR bits 3 and 2 occurs at the POE1 pin • Bit 12—POE0 Flag (POE0F): This flag indicates that a high impedance request has been input to the POE0 pin.
• Bits 5 and 4—POE2 Mode 1, 0 (POE2M1 and POE2M0): These bits select the input mode of the POE2 pin. Bit 5: POE2M1 Bit 4: POE2M0 Description 0 0 Accept request on falling edge of POE2 input. (initial value) 1 Accept request when POE2 input has been sampled for 16 φ/8 clock pulses, and all are low level. 0 Accept request when POE2 input has been sampled for 16 φ/16 clock pulses, and all are low level.
12.10.2 Output Level Control/Status Register (OCSR) The output level control/status register (OCSR) is a 16-bit read/write register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. OCSR is initialized to H'0000 by an external power-on reset; however, it is not initialized for manual resets, reset by WDT standby mode, or sleep mode, so the previous data is maintained.
• Bit 9—Output Level Compare Enable (OCE): This bit enables the start of output level comparisons. When setting this bit, pay special attention to the output pin combinations shown in table 12.19. When 0 is output, the OSF bit is set to 1 at the same time this bit is set, and output goes to high impedance. Accordingly, bits 15–11 and bit 9 of the port E data register (PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU’s output pins with the PFC.
12.11 Operation 12.11.1 Input Level Detection Operation If the input conditions set by the ICSR occur on any of the POE pins, all high-current pins become high-impedance state. Falling Edge Detection: When a change from high to low level is input to the POE pins. Low-Level Detection: Figure 12.126 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR.
12.11.2 Output-Level Compare Operation Figure 12.127 shows an example of the output-level compare operation for the combination of PE09/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations. CK 0 level overlapping detected PE09/ TIOC3B PE11/ TIOC3D High impedance state Figure 12.127 Output-Level Detection Operation 12.11.
12.11.4 POE timing Figure 12.128 shows an example of timing from POE input to high impedance of pin. CK CK last transition POE input Last transition edge detected PE9/TIOC3B High impedance state* Note: * Other high current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C/DACK0/AH, PE15/TIOC4D/DACK1/IRQOUT) will enter the high impedance state with the same timing. Figure 12.128 Last Transition Edge Detection Operation 12.11.
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Section 13 Watchdog Timer (WDT) 13.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer.
13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. Overflow Interrupt control Clock WDTOVF Clock select Reset control Internal reset signal* RSTCSR TCNT TCSR Bus interface Module bus TCSR: TCNT: RSTCSR: Note: φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources Internal data bus ITI (interrupt signal) WDT Timer control/status register Timer counter Reset control/status register * The internal reset signal can be generated by setting the register.
13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 WDT Registers Address Write* R/(W)*3 H'18 H'FFFF8610 TCNT R/W H'00 RSTCSR R/(W)*3 H'1F Abbreviation R/W Timer control/status register TCSR Timer counter Reset control/status register Read* 2 Initial Value Name 1 H'FFFF8610 H'FFFF8611 H'FFFF8612 H'FFFF8613 Notes: *1 Write by word transfer.
13.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a power-on reset or in standby mode. Bits 2–0 are initialized to 000 by a power-on reset, but retain their values in the standby mode.
• Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description 0 Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) 1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. • Bits 4 and 3—Reserved: These bits always read as 1. The write value should always be 1. • Bits 2–0: Clock Select 2–0 (CKS2–CKS0): These bits select one of eight internal clock sources for input to the TCNT.
13.2.3 Reset Control/Status Register (RSTCSR) The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers in that it is more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type.
13.2.4 Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. The TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word.
Writing 0 to the WOVF bit 15 Address: H'FFFF8612 8 7 H'A5 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'FFFF8612 8 H'5A 7 0 Write data Figure 13.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR, H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR. 13.3 Operation 13.3.
TCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128 φ clocks Internal reset signal* WT/IT: Timer mode select bit TME: Timer enable bit 512 φ clocks Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 13.
13.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5). TCNT value Overflow H'FF Overflow Overflow Overflow H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI ITI: Interval timer interrupt request generation Figure 13.5 Operation in the Interval Timer Mode 13.3.
13.3.4 Timing of Setting the Overflow Flag (OVF) In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and an interval timer interrupt is simultaneously requested (figure 13.6). CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of Setting the OVF 13.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output.
13.4 Notes on Use 13.4.1 TCNT Write and Increment Contention If a timer counter (TCNT) increment clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.8 Contention between TCNT Write and Increment 13.4.
13.4.4 System Reset With WDTOVF If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. SH7040 Series Reset input Reset signal to entire system RES WDTOVF Figure 13.9 Example of a System Reset Circuit with a WDTOVF Signal 13.4.
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Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7040 Series has a serial communication interface (SCI) with two independent channels, both of which possess the same functions. The SCI supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 14.1.1 Features • Select asynchronous or clock synchronous as the serial communications mode.
14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the SCI.
14.1.3 Pin Configuration Table 14.1 summarizes the SCI pins by channel. Table 14.
14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR. The CPU cannot read or write the RSR directly. 14.2.
The CPU cannot read or write the TSR directly. 14.2.4 Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — Transmit Data Register (TDR) The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission.
• Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or clock synchronous mode. Bit 7: C/A Description 0 Asynchronous mode (initial value) 1 Clocked synchronous mode • Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 Eight-bit data (initial value) 1 Seven-bit data.
• Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
14.2.6 Serial Control Register (SCR) The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a power-on reset or in standby mode. Manual reset does not initialize SCR.
• Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter disabled (initial value). The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 1 Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1.
• Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) requests are disabled.* (initial value) 1 Transmit-end interrupt (TEI) requests are enabled.
14.2.7 Serial Status Register (SSR) The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
• Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data.
• Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Bit 4: FER Description 0 Receiving is in progress or has ended normally (initial value). Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value.
• Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written.
14.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset or in standby mode. Each channel has independent baud rate generator control, so different values can be set in the two channels.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 7.3728 8 9.8304 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 130 –0.07 2 141 0.03 2 174 –0.26 150 2 95 0.00 2 103 0.16 2 127 0.00 300 1 191 0.00 1 207 0.16 1 255 0.00 600 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 23 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 10 11.0592 12 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 177 –0.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 –1.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 12.288 14 14.7456 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 16 17.2032 18 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 70 0.03 3 75 0.48 3 79 –0.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 18.432 19.6608 20 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 81 –0.22 3 86 0.31 3 88 –0.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 22 22.1184 24 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 97 –0.35 3 97 0.19 3 106 –0.44 150 3 71 –0.54 3 71 0.00 3 77 0.16 300 2 142 0.16 2 143 0.00 2 155 0.16 600 2 71 –0.54 2 71 0.00 2 77 0.16 1200 1 142 0.16 1 143 0.00 1 155 0.16 2400 1 71 –0.54 1 71 0.00 1 77 0.16 4800 0 142 0.16 0 143 0.00 0 155 0.16 9600 0 71 –0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 24.576 25.8048 26 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 108 0.08 3 114 –0.40 3 114 0.36 150 3 79 0.00 3 83 0.00 3 84 –0.43 300 2 159 0.00 2 167 0.00 2 168 0.16 600 2 79 0.00 2 83 0.00 2 84 –0.43 1200 1 159 0.00 1 167 0.00 1 168 0.16 2400 1 79 0.00 1 83 0.00 1 84 –0.43 4800 0 159 0.00 0 167 0.00 0 168 0.16 9600 0 79 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 27.0336 28 29.4912 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 119 0.00 3 123 0.23 3 130 -0.07 150 3 87 0.00 3 90 0.16 3 95 0.00 300 2 175 0.00 2 181 0.16 2 191 0.00 600 1 87 0.00 2 90 0.16 2 95 0.00 1200 1 175 0.00 1 181 0.16 1 191 0.00 2400 1 87 0.00 1 90 0.16 1 95 0.00 4800 0 175 0.00 0 181 0.16 0 191 0.00 9600 0 87 0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 30 31.9488 32 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 132 0.13 3 141 -0.13 3 141 0.03 150 3 97 -0.35 3 103 0.00 3 103 0.16 300 2 194 0.16 2 207 0.00 2 207 0.16 600 2 97 -0.35 2 103 0.00 2 103 0.16 1200 1 194 0.16 1 207 0.00 1 207 0.16 2400 1 97 -0.35 1 103 0.00 1 103 0.16 4800 0 194 0.16 0 207 0.00 0 207 0.16 9600 0 97 -0.
Table 14.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 33 33.1776 33.3333 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 145 0.33 3 146 0.19 3 147 -0.02 150 3 106 0.39 3 107 0.00 3 108 -0.45 300 2 214 -0.07 2 215 0.00 2 216 0.01 600 2 106 0.39 2 107 0.00 2 108 -0.45 1200 1 214 -0.07 1 215 0.00 1 216 0.01 2400 1 106 0.39 1 107 0.00 1 108 -0.45 4800 0 214 -0.07 0 215 0.00 0 216 0.
Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode φ (MHz) 4 Bit Rate (Bits/s) n N 110 3 141 250 2 500 8 10 12 n N n N n N 249 3 124 3 155 3 187 2 124 2 249 3 77 3 93 1k 1 249 2 124 2 155 2 187 2.
Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode (cont) φ (MHz) Bit Rate (Bits/s) 16 n N 250 3 249 500 3 1k 20 24 28 n N n N n N 124 3 155 3 187 3 218 2 249 3 77 3 93 3 108 2.
Table 14.4 Bit Rates and BRR Settings in Clocked Synchronous Mode (cont) φ (MHz) 30 Bit Rate (Bits/s) 32 n N n N 500 3 233 3 249 1k 3 116 3 2.5k 2 187 5k 2 10k 33 33.
B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n Clock Source CKS1 CKS2 0 φ 0 0 1 φ/4 0 1 2 φ/16 1 0 3 φ/64 1 1 The bit rate error in asynchronous mode is calculated as follows: Error (%) = φ × 106 (N+1) × B × 64 × 2 2n–1 –1 × 100 Table 14.
Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (Bits/s) n N 4 125000 0 0 4.9152 153600 0 0 6 187500 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.
Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 4 1.0000 62500 4.9152 1.2288 76800 6 1.5000 93750 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 11.0592 2.7648 172800 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 18.432 4.6080 288000 19.6608 4.
Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 33.3333 5.5556 5555550.
14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 14.8.
Table 14.
14.3.2 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Transmit/Receive Formats: Table 14.10 shows the 11 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 14.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.
Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) 1 Select transmit/receive format in SMR 2 Set value to BRR 3 Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary 4 End Figure 14.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 14.5 shows a sample flowchart for transmitting serial data.
Initialize 1 Start transmitting Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmission data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? No Yes Read TEND bit in SSR No TEND = 1? Yes No Output break signal? 4 Yes Set DR = 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC End transmission Figure 14.
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting.
1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle (marking state) TDRE TEND TxI TxI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 TxI request TEI interrupt request 1 frame Example: 8-bit data with parity and one stop bit Figure 14.6 SCI Transmit Operation in Asynchronous Mode Receiving Serial Data (Asynchronous Mode): Figures 14.7 and 14.
Initialization 1 Start reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Yes 2 Error handling No Read the RDRF bit in SSR No 3 RDRF = 1? Yes Read reception data of RDR and clear RDRF bit in SSR to 0 No 4 All data received? Yes Clear the RE bit of SCR to 0 End reception Figure 14.
Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit in SCR to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 14.
In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR. b. Stop bit check.
1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle (marking state) TDRF RxI interrupt request FER 1 frame RxI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Example: 8-bit data with parity and one stop bit. Figure 14.9 SCI Receive Operation 14.3.
Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 14.8. Clock: See the description in the asynchronous mode section.
Initialization 1 Start transmission Read TDRE bit in SSR TDRE = 1? 2 No Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? No 3 Yes Read TEND bit in SSR TEND = 1? No Yes Output break signal? No Yes Set DR = 0 4 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC End transmission Figure 14.
In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting.
1 Multiprocessor bit Stop Start Data bit bit Start bit Serial data 0 D0 D1 D7 0/1 1 0 Multiprocessor bit Stop Data bit D0 D1 D7 0/1 1 1 Idle (marking state) TDRE TEND TxI interrupt request TxI interrupt handler writes data in TDR and clears TDRE to 0 TxI interrupt request TEI interrupt request 1 frame Example: 8-bit data with multiprocessor bit and one stop bit Figure 14.12 SCI Multiprocessor Transmit Operation Receiving Multiprocessor Serial Data: Figure 14.
Initialization 1 Start reception Set MPIE bit in SCR to 1 2 Read ORER and FER bits of SSR FER = 1? or ORER =1? Yes No Read RDRF bit in SSR No 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station’s ID Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? Yes No Read RDRF bit of SSR RDRF = 1? 5 No Yes Read receive data from RDR 4 No All data received? Error processing Yes Clear RE bit in SCR to 0 End reception Figure 14.
Start error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCR to 0 Clear ORER and FER bits in SSR to 0 End Figure 14.
Figures 14.14 and 14.15 show examples of SCI receive operation using a multiprocessor format. 1 Serial data Start bit Data (ID1) 0 D0 D1 Stop Start Data MPB bit bit (data 1) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RxI interrupt request (multiprocessor interrupt), MPIE = 0 RxI interrupt handler reads data in RDR and clears RDRF to 0 Not station’s ID, so MPIE is set to 1 again No RxI interrupt, RDR maintains state Figure 14.
1 Serial data Start bit 0 Data (ID2) D0 D1 Stop Start Data MPB bit bit (data 2) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RxI interrupt request (multiprocessor interrupt), MPIE = 0 ID2 RxI interrupt handler reads data in RDR and clears RDRF to 0 Data2 Station’s ID, so receiving MPIE continues, with data bit is again received by the RxI set to 1 interrupt processing routine Example: Own ID matches data, 8-bit data with multiprocessor bit and on
Transfer direction One unit (character or frame) of communication data Synchronization clock * * LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 14.16 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock.
Figure 14.17 is a sample flowchart for initializing the SCI. 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.
Transmitting Serial Data (Synchronous Mode): Figure 14.18 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3.
Initialize 1 Start transmitting 2 Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? No Yes Clear TE bit to 0 in SCR End Figure 14.
Figure 14.19 shows an example of SCI transmit operation. Transmit direction Synchronization clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TxI request TxI interrupt handler writes data in TDR and clears TDRE to 0 TxI request TEI request 1 frame Figure 14.19 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in the SSR.
Receiving Serial Data (Clock Synchronous Mode): Figures 14.20 and 14.21 shows a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is listed below: 1. SCI initialization: Set the RxD pin using the PFC. 2.
Initialization 1 Start reception Read the ORER bit of SSR Yes ORER = 1? 2 No Read RDRF bit of SSR No Error processing 3 RDRF = 1? Yes Read receive data from RDR and clear RDRF bit of SSR to 0 4 No All data received? Yes Clear RE bit of SCR to 0 End reception Figure 14.
Error handling Overrun error processing Clear ORER bit of SSR to 0 End Figure 14.21 Sample Flowchart for Serial Receiving (2) Figure 14.22 shows an example of the SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RxI request Read data with RxI interrupt processing routine and clear RDRF bit to 0 RxI request ERI interrupt request generated by overrun error 1 frame Figure 14.
to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RxI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI).
Initialization 1 Start transmitting/receive Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmission data in TDR and clear TDRE bit of SSR to 0 Read ORER bit of SSR ORER = 1? Yes 3 Error handling No Read RDRF bit of SSR No 4 RDRF = 1? Yes Read receive data of RDR, and clear RDRF bit of SSR to 0 No 5 All data transmitted/and received Yes Clear TE and RE bits of SCR to 0 End transmission/reception Figure 14.
14.4 SCI Interrupt Sources and the DMAC/DTC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RxI), and transmit-data-empty (TxI). Table 14.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TxI is requested when the TDRE bit in the SSR is set to 1.
14.5 Notes on Use Sections 14.5.1 through 14.5.9 provide information for using the SCI. 14.5.1 TDR Write and TDRE Flags The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status.
14.5.3 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 14.5.
16 clocks 8 clocks Internal 0 base clock 78 15 0 –7.5 clocks Receive data (RxD) 78 15 0 5 +7.5 clocks D0 Start bit D1 Synchronization sampling timing Data sampling timing Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as: M = 0.5 – 1 – (L – 0.5)F – 2N D – 0.5 N (1 + F) × 100% M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0–1.
14.5.7 Constraints on DMAC/DTC Use • When using an external clock source for the synchronization clock, update the TDR with the DMAC or the DTC, and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 14.25). • Before reading the receive data register (RDR) with the DMAC/DTC, select the receive-datafull interrupt of the SCI as a start-up source.
Section 15 High Speed A/D Converter (Excluding A Mask) 15.1 Overview The high speed A/D converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 15.1.1 Features The high speed A/D converter has the following features: • 10-bit resolution • Eight input channels • Analog conversion voltage range setting is selectable Using the reference voltage pin (AVref) as an analog standard voltage (Vref), conversion of analog input from 0 to Vref (only with SH7043).
15.1.2 Block Diagram Figure 15.1 is the block diagram of the high speed A/D converter.
Table 15.
15.2 Register Descriptions 15.2.1 A/D Data Registers A–H (ADDRA–ADDRH) The ADDR are 16-bit read only registers for storing A/D conversion results. There are eight of these registers, ADDRA through ADDRH. The A/D converted data is 10-bit data which is sent to the ADDR for the corresponding converted channel for storage. The lower 8 bits of the A/D converted data are transferred to and stored in the lower byte (bits 7–0) of the ADDR, and the upper 2 bits are stored into the upper byte (bits 9, 8).
Table 15.3 Analog Input Channel and ADDR Correspondence Analog Input Channel A/D Data Register AN0 ADDRA* AN1 ADDRB* AN2 ADDRC* AN3 ADDRD* AN4 ADDRE AN5 ADDRF AN6 ADDRG AN7 ADDRH Note: * Except during buffer operation 15.2.2 A/D Control/Status Register (ADCSR) The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to indicate status. The ADCSR is initialized to H'00 by power-on reset or in standby mode. Manual reset does not initialize ADCSR.
• Bit 7—A/D End Flag (ADF): This status flag indicates that A/D conversion has ended.
• Bit 4—Clock Select (CKS): Sets the A/D conversion time. Set, according to the operating frequency, to give a conversion time of at least 2 µs (5 V version) or 4 µs (3.3 V version). Make conversion time changes only while conversion is halted.
15.2.3 A/D Control Register (ADCR) The ADCR is an 8-bit read/write register used for A/D conversion operation control. The ADCR is initialized to H'00 by power-on reset or in standby mode. Manual reset does not initialize. Bit: 7 6 5 4 3 2 1 0 — PWR TRGS1 TRGS0 SCAN DSMP BUFE1 BUFE0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W • Bit 7—Reserved: This bit always reads as 0. The write value should always be 0.
• Bit 2—Simultaneous Sampling (DSMP): Enables or disables the simultaneous sampling of two channels. See section 15.4.6, Simultaneous Sampling Operation, for details on simultaneous sampling. Set the DSMP bit only while conversion is halted. Bit 2: DSMP Description 0 Normal sampling operation (initial value) 1 Simultaneous sampling operation • Bits 1–0—Buffer Enable 1, 0 (BUFE1, BUFE0): These bits select whether to use the ADDRB–ADDRD as buffer registers.
Word data read Data register Bus I/F 0 0 0 0 Internal data bus Upper 8 bits 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 Lower 8 bits AD 3 AD 2 AD 1 AD 0 Figure 15.
Byte data read Data register Bus I/F 0 0 0 Internal data bus 0 Upper 8 bits 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Figure 15.
15.4 Operation • The high speed A/D converter has 10-bit resolution. • In addition to the four operating modes of select or group, and single or scan can be set in combination with buffer operation and simultaneous sampling operation. • Select mode uses one channel and group mode selects multiple channels. • One start in the single mode performs conversions on all selected channels, and one start in the scan mode performs repeated conversions until stopped by software.
ADF Set to 1 by software ADST Channel 0 Channel 1 Automatic clear Conversion standby Conversion A/D Conversion Sampling 1 standby conversion 1 standby Channel 2 Conversion standby Channel 3 Conversion standby ADDRA ADDRB Conversion result 1 ADDRC ADDRD Figure 15.4 A/D Converter Operation Example (Select-Single Mode) 15.4.2 Select-Scan Mode Choose select-scan mode when doing repeated A/D conversions for one channel.
ADF ADST Channel 0 Set to 1 by software Cleared to 0 by software Conversion standby A/D conversion 5 Channel 1 ConverSampling sion 1 standby A/D conversion 1 Sampling 3 A/D conversion 3 Sampling 5 Conversion standby Sampling 2 A/D conversion 2 Sampling 4 A/D conversion 4 Conversion stopped Sampling 6 Channel 2 Conversion standby Channel 3 Conversion standby ADDRA ADDRB Conversion result 1 Conversion result 2 Conversion result 3 Conversion result 4 ADDRC ADDRD Figure 15.
ADF ADST Channel 0 Channel 1 A/D Conversion Sampling conversion Conversion standby standby 1 1 Conversion standby Channel 2 Conversion standby Channel 3 Automatic clear Set to 1 by software A/D Sampling conversion 2 2 Sampling 3 Conversion standby A/D Conversion conversion standby 3 Conversion standby ADDRA ADDRB ADDRC Conversion result 1 Conversion result 2 Conversion result 3 ADDRD Figure 15.6 A/D Converter Operation Example (Group-Single Mode) 15.4.
Figure 15.7 shows an example of operation in the group-scan mode when AN0–AN2 are selected.
To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10, and CH2 = 0. Buffer operation timing is shown in figure 15.8.
When the ADF flag is set to 1, if the ADIE bit is also set to 1, an ADI interrupt is issued. After the ADCSR is read, the ADF flag is cleared by a 0 write. With select single mode, the A/D converter goes into standby mode at the end of every conversion cycle. The A/D converter is restarted by software, a timer trigger, or external trigger. When the number of conversion cycles shown in table 15.4 have ended, the ADF flag is set to 1. Table 15.
Table 15.
Table 15.
15.4.7 Conversion Start Modes The conversion start mode of the high speed A/D converter is set by the PWR bit of the ADCSR. When the PWR bit is cleared to 0, low-power conversion mode is set and the internal analog circuit becomes inactive. High-speed start mode is set by setting the PWR bit to 1, and the analog circuit becomes active. In the low-power conversion mode, power is applied to the analog circuitry simultaneous to the conversion start (ADST set).
Figures 15.10 and 15.11 show examples of conversion start operation timing. ADF Analog circuit power supply Set ADST Clear Set to 1 by software Channel 0 Conversion standby Channel 1 Conversion standby Channel 2 Conversion standby Channel 3 Conversion standby Sampling 1 Cleared to 0 by software A/D conversion 1 Sampling 3 Sampling 2 A/D conversion 2 A/D conversion 3 200 cycles ADDRA ADDRB Conversion result 1 Conversion result 3 Conversion result 2 ADDRC ADDRD Figure 15.
ADF Analog circuit power supply (PWR cleared to 0) Switched on by software (PWR set to 1) ADST Switched off by software Set to 1 by software Set to 1 by software Channel 0 Conversion standby Channel 1 Conversion standby Channel 2 Conversion standby Channel 3 Conversion standby Sampling 1 A/D conversion 1 Sampling 2 A/D conversion 2 200 cycles Conversion result 2 ADDRA Conversion result 1 ADDRB ADDRC ADDRD Figure 15.
15.4.8 Conversion Start by External Input A/D conversions can be started by trigger signals generated by timer conversion start triggers or ADTRG inputs. When a trigger signal designated by the TRGS1 and TRGS0 bits of the ADCR occurs, the ADST bit of the ADCSR is set to 1 and A/D conversion is started. The other operations are the same as when the ADST bit is set to 1 by software. Figure 15.12 shows an example of the timing when the ADST bit is set by an external input.
15.4.9 A/D Conversion Time The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D converter samples the input at time t D after the ADST bit is set to 1, and then starts the conversion. The A/D conversion time tCONV is the sum of the conversion start delay time tD, the input sampling time tSPL, and the operating time tCP. This conversion time is not a set value, but is decided by the tD ADCSR write timing, or the timer conversion start trigger generation timing. Figure 15.
Table 15.7 A/D Conversion Times CKS = 0 CKS = 1 Time Symbol Min Typ Max Min Typ Max A/D conversion start delay time tD 1.5 1.5 1.5 1.5 1.5 1.5 Input sampling time t SPL 20 20 20 40 40 40 A/D conversion time t CONV 42.5 42.5 42.5 82.5 82.5 82.5 Notes: 1. Unit: states 2. Table entries are for when ADST = 1. If 200 states have not elapsed since the PWR bit has been set, no conversions are done until after those 200 states have occurred.
When the DTC or DMAC are activated by an ADI interrupt, the ADF flag is cleared to 0 when the final specified data register is read. Table 15.9 High Speed A/D Converter Interrupt Sources Interrupt Source Description DTC, DMAC Activation ADI Interrupt caused by conversion end Possible 15.6 Notes on Use Take note of the following for the A/D converter. 1.
AVcc AVref This LSI 100Ω Rin*2 AN0 to AN7 *1 0.1µF *1 AVss Notes: Numbers are only to be noted as reference value *1 10µF 0.01µF *2 Rin: Input impedance Figure 15.14 Example of a Protection Circuit for the Analog Input Pins 1.0kΩ AN0 to AN7 20pF Analog multiplexer 1MΩ High-speed A/D converter Note: Numbers are only to be noted as reference value Figure 15.
Table 15.
566
Section 16 Mid-Speed A/D Converter (A Mask) 16.1 Overview The mid-speed A/D converter has 10 bit resolution, and can select from a maximum of eight channels of analog input. The mid-speed A/D converter is structured by two independent modules (A/D0 and A/D1) 16.1.
16.1.2 Block Diagram Figure 16.1 is the block diagram of the mid-speed A/D converter. AVCC, AVref and AVSS pins of both A/D are common in LSI.
16.1.3 Pin Configuration Table 16.1 shows the input pins used with the mid-speed A/D converter. The AVCC and AVSS pins are for the mid-speed A/D converter internal analog section power supply. AVref pin is the A/D conversion standard voltage. Table 16.
16.1.4 Register Configuration Table 16.2 shows the register configuration of the mid-speed A/D converter. Table 16.
16.2 Register Descriptions 16.2.1 A/D Data Register A–D (ADDRA0–ADDRD0, ADDRA1–ADDRD1) A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are eight registers: ADDRA0–ADDRD0 (A/D0) and ADDRA1–ADDRD1 (A/D1). The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted channel for storage. The upper 8 bits of the A/D converted data correspond to the upper byte of the ADDR and the lower 2 bits correspond to the lower byte.
16.2.2 A/D Control/Status Register (ADCSR0, ADCSR1) The A/D control/status registers (ADCSR0, 1) are registers that can read/write in 8 bits and control A/D converter operations such as mode selection. There are the ADCSR0 (A/D0) and ADCSR1 (A/D1). The ADCSR is initialized to H'00 during power-on reset or standby mode. Manual reset does not initialize ADCSR.
• Bit 5—A/D Start (ADST): Selects start/end of A/D conversion. A1 is maintained during A/D conversion start. It is also possible to set a 1 by the A/D conversion trigger input pin (ADTRG). Bit 5: ADST Description 0 A/D conversion halted 1 1. Single mode: Starts A/D conversion. Automatically clears to 0 when conversion of the designated channel is complete (Initial value) 2. Scan mode: Starts A/D conversion.
Channel Selection Description Single mode Scan mode CH1 CH0 A/D0 A/D1 A/D0 A/D1 0 0 AN0 (Initial value) AN4 (Initial value) AN0 AN4 1 AN1 AN5 AN0, AN1 AN4, AN5 0 AN2 AN6 AN0, AN1 AN4–AN6 1 AN3 AN7 AN0–AN3 AN4–AN7 1 16.2.3 A/D Control Register (ADCR0, ADCR1) A/D control registers (ADCR0, 1) are registers that can read/write in 8 bits and enables or disables A/D conversion start of the external trigger input. There are the ADCR0 (A/D0) and ADCR1 (A/D1).
16.3 Interface with CPU Although A/D data register ADDR (ADDRA0–ADDRD0, ADDRA1–ADDRD1) are 16-bit registers, the bus width within the chip that integrates with the CPU is 8-bits. So, upper and lower data of the ADDR must be read separately. To avoid change in data while reading the upper/lower 2 bytes of ADDR, the lower byte data is read through the temporary register (TEMP). The upper byte data can be read directly.
16.4 Operation The mid-speed converter operates using the continuous comparison method and is equipped with 10-bit resolution. Operations for the single and scan modes are explained below. 16.4.1 Single Mode (SCAN=0) The single mode is selected when executing A/D conversion for one channel only. A/D conversion is initiated when the ADST bit of the A/D control/status register is set to 1 by the software or external trigger input.
Figure 16.
16.4.2 Scan Mode (SCAN=1) The scan mode is optimal for monitoring analog input of multiple channels (including channel 1). A/D conversion is started from channel 1 (AN0 for A/D0 and AN4 for A/D1) of the group when the ADST bit of the A/D control/status register (ADCSR) is set to 1 by the software or external trigger input. When multiple channels are selected, A/D conversion of channel 2 (AN1 or AN5) is initiated immediately after completion of the channel 1 conversion.
Figure 16.
16.4.3 Input Sampling and A/D Conversion Time The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D converter samples input after t D hours has elapsed since setting the ADST bit of the A/D control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is shown in table 16.4. The A/D conversion time, as shown in figure 16.5, includes both tD and input sampling time. Here, tD is determined by the write timing to ADCSR and is not constant.
Table 16.4 A/D Conversion Time (Single Mode) CKS=0 Notation Min CKS=1 Typ Max Min Typ Max A/D conversion start delay time t D 10 — 17 6 — 9 Input sampling time t SPL — 64 — — 32 — A/D conversion time t CCNV 259 — 266 131 — 134 Note: Numbers in the table are in states (t cyc ). 16.4.4 External Trigger Input Timing It is possible to start A/D conversion from an external trigger input.
16.5 Interrupt and DMA, DTC Transfer Requests The mid-speed A/D converter generates A/D conversion complete interrupt when completing A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit of ADCSR. It is also possible to activate DMA or DTC transfer by the ADI interrupt request. It is possible to activate DTC with ADI0 interrupt of A/D0 and activate DMAC with ADI1 interrupt of A/D1. Table 16.5 shows the interrupt factors of the mid-speed A/D converter. Table 16.
16.6 A/D Conversion Precision Definitions The medium-speed A/D converter converts analog values input from analog input channels to 10bit digital values by comparing them with an analog reference voltage. In this operation, the absolute precision of the A/D conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error.
16.7 Usage Notes The following points should be noted when using the mid-speed A/D converter. 16.7.1 Analog Voltage Settings (1) Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVref (n = 0 to 7). (2) AVCC and AVSS input voltages For the AV CC and AVSS input voltages, set AVCC = VCC ±10% and AVSS = VSS . When the medium-speed A/D converter is not used, set AVCC = VCC and AVSS = VSS .
AVCC AVref Rin*2 *1 This LSI 100 Ω AN0–AN15 *1 0.1 µF AVSS Notes: Numbers are only to be noted as reference value *1 10 µF 0.01 µF *2 Rin: Input impedance Figure 16.
1.0kΩ AN0 to AN7 20pFΩ Analog multiplexer 1MΩ Mid-speed A/D converter Note : Numbers are only to be noted as reference value Figure 16.9 Equivalent Circuit for the Analog Input Pins Table 16.
Section 17 Compare Match Timer (CMT) 17.1 Overview The SH7040 series has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 17.1.1 Features The CMT has the following features: • Four types of counter input clock can be selected One of four internal clocks (φ/8, φ/32, φ/128, φ/512) can be selected independently for each channel.
Control circuit Clock selection CMCNT0 Module bus CMCNT1 Clock selection Comparator Control circuit CMCOR1 φ/8 φ/32 φ/128 φ/512 CMCSR1 CMI1 Comparator φ/8 φ/32 φ/128 φ/512 CMCOR0 CMCSR0 CMSTR CM10 Bus interface CMT Internal bus CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 17.
17.1.3 Register Configuration Table 17.1 summarizes the CMT register configuration. Table 17.
17.2 Register Descriptions 17.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by power-on resets and by standby mode. Manual reset does not initialize CMSTR.
17.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode. Manual reset does not initialize CMCSR.
• Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (φ). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 φ/8 (initial status) 1 φ/32 0 φ/128 1 φ/512 1 17.2.
17.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets and by standby mode. There is no initializing with manual reset.
17.3.2 CMCNT Count Timing One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be selected by the CKS1, CKS0 bits of the CMCSR. Figure 17.3 shows the timing. CK Internal clock CMCNT input clock CMCNT N–1 N N+1 Figure 17.3 Count Timing 17.4 Interrupts 17.4.1 Interrupt Sources and DTC Activation The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them.
CK CMCNT input clock CMCNT N CMCOR N 0 Compare match signal CMF CMI Figure 17.4 CMF Set Timing 17.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a clear signal after a DTC transfer. Figure 17.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 CK CMF Figure 17.
17.5 Notes on Use Take care that the contentions described in sections 17.5.1–17.5.3 do not arise during CMT operation. 17.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 17.6 shows the timing. CMCNT write cycle T1 T2 CK Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 17.
17.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T 2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 17.7 shows the timing. CMCNT write cycle T1 T2 CK Address CMCNT Internal write signal Compare match signal CMCNT N M CMCNT write data Figure 17.
17.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T 2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 17.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle.
Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. Table 18.1 lists the SH7040 Series’s multiplexed pins. The multiplex pin functions have restrictions dependent on the operating mode. Table 18.2 lists the pin functions and initial values for each operating mode. Table 18.
Table 18.
Table 18.
Table 18.
Table 18.
604 Single Chip Mode — 4 5 6 7 8 9 10 11 12 13 14 15 16 — — — — — — — — — — — — — — — 70 69 68 67 66 64 63 62 60 59 58 57 56 54 53 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PD16/D16/IRQ0 PD17/D17/IRQ1 PD18/D18/IRQ2 PD19/D19/IRQ3 PD20/D20/IRQ4 PD21/D21/IRQ5 PD22/D22/IRQ6 PD23/D23/IRQ7 PD24/D24/DREQ0 PD25/D25/DREQ1 PD26/D26/DACK0 PD27/D27/DACK1 PD28/D28/CS2 PD29/D29/CS3 PD30/D30/IRQOUT PD31/D31/ADTRG A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D1
605 TFP120 18 19 20 21 23 25 26 27 29 32 33 34 35 54 53 52 51 50 49 48 47 46 45 44 43 41 39 37 88 — — — — — — — — 85 87 79 77 86 81 89 88 84 83 80 78 82 107 104 Pin NO.
606 TFP120 — 98 99 100 101 102 103 105 106 92 93 94 95 96 109 112 113 114 115 116 118 119 120 2 3 Pin NO.
18.2 Register Configuration Table 18.3 summarizes the registers of the pin function controller. Table 18.
18.3 Register Descriptions 18.3.1 Port A I/O Register H (PAIORH) The port A I/O register H (PAIORH) is a 16-bit read/write register that selects input or output for the most significant 8 pins of port A. Bits PA23IOR–PA16IOR correspond to pins PA23/WRHH– PA16/AH. PAIORH is enabled when the port A pins function as general input/outputs (PA23– PA16). For other functions, it is disabled.
18.3.2 Port A I/O Register L (PAIORL) The port A I/O register L (PAIORL) is a 16-bit read/write register that selects input or output for the least significant 16 pins of port A. Bits PA15IOR–PA0IOR correspond to pins PA15/CK– PA0/RXD0. PAIORL is enabled when the port A pins function as general input/outputs (PA15– PA0), or with the serial clock (SCK1, SCK0). For other functions, it is disabled.
The settings for this register are effective only for the 144-pin version. There are no corresponding pins for this register in the 112-pin and 120-pin versions. However, read/writes are possible.
• Bit 8—PA20 Mode (PA20MD): Selects the function of the PA20/CASHL pin. Bit 8: PA20MD Description 0 General input/output (PA20) (initial value) 1 Column address output (CASHL) (PA20 in single chip mode) • Bits 7 and 6—PA19 Mode 1, 0 (PA19MD1 and PA19MD0): These bits select the function of the PA19/BACK/DRAK1 pin.
• Bit 0—PA16 Mode (PA16MD): Selects the function of the PA16/AH pin. Bit 0: PA16MD Description 0 General input/output (PA16) (initial value) 1 Address hold output (AH) (PA16 in single chip mode) 18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2) PACRL1 and PACRL2 are 16-bit read/write registers that select the functions of the least significant sixteen multiplexed pins of port A.
• Bit 14—PA15 Mode (PA15MD): Selects the function of the PA15/CK pin. Bit 14: PA15MD Description 0 General input/output (PA15) (single chip mode initial value) 1 Clock output (CK) (extended mode initial value) • Bit 13—Reserved: This bit always reads as 0. The write value should always be 0. • Bit 12—PA14 Mode (PA14MD): Selects the function of the PA14/RD pin.
• Bit 4—PA10 Mode (PA10MD): Selects the function of the PA10/CS0 pin. Bit 4: PA10MD Description 0 General input/output (PA10) (initial value) (CS0 in on-chip ROM invalid mode) 1 Chip select output (CS0) (PA10 in single chip mode) • Bits 3 and 2—PA9 Mode 1, 0 (PA9MD1 and PA9MD0): These bits select the function of the PA9/TCLKD/IRQ3 pin.
Port A Control Register L2 (PACRL2): Bit: 15 14 13 12 11 10 9 8 PA7 MD1 PA7 MD0 PA6 MD1 PA6 MD0 PA5 MD1 PA5 MD0 — PA4MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W 7 6 5 4 3 2 1 0 — PA3MD PA2 MD1 PA2 MD0 — PA1MD — PA0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R R/W Initial value: R/W: Bit: • Bits 15 and 14—PA7 Mode 1, 0 (PA7MD1 and PA7MD0): These bits select the function of the PA7/TCLKB/CS3 pin.
• Bits 11 and 10—PA5 Mode 1, 0 (PA5MD1 and PA5MD0): These bits select the function of the PA5/SCK1/DREQ1/IRQ1 pin. Bit 11: PA5MD1 Bit 10: PA5MD0 Description 0 0 General input/output (PA5) (initial value) 1 Serial clock input/output (SCK1) 0 DMA transfer request received input (DREQ1) (PA5 in single chip mode) 1 Interrupt request input (IRQ1) 1 • Bit 9—Reserved: This bit always reads as 0. The write value should always be 0. • Bit 8—PA4 Mode (PA4MD): Selects the function of the PA4/TxD1 pin.
• Bit 2—PA1 Mode (PA1MD): Selects the function of the PA1/TxD0 pin. Bit 2: PA1MD Description 0 General input/output (PA1) (initial value) 1 Transmit data output (TxD0) • Bit 1—Reserved: This bit always reads as 0. The write value should always be 0. • Bit 0—PA0 Mode (PA0MD): Selects the function of the PA0/RxD0 pin. Bit 0: PA0MD Description 0 General input/output (PA0) (initial value) 1 Receive data input (RxD0) 18.3.
18.3.6 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the ten multiplexed pins of port B. PBCR1 selects the functions of the top two bits of port B; PBCR2 selects the functions of the bottom eight bits of port B.
• Bits 1 and 0—PB8 Mode (PB8MD1 and PB8MD0): PB8MD1 and PB8MD0 select the function of the PB8/IRQ6/A20/WAIT pin.
• Bits 13 and 12—PB6 Mode (PB6MD1 and PB6MD0): PB6MD1 and PB6MD0 select the function of the PB6/IRQ4/A18/BACK pin. Bit 13: PB6MD1 Bit 12: PB6MD0 Description 0 0 General input/output (PB6) (initial value) 1 Interrupt request input (IRQ4) 0 Address output (A18) (PB6 in single chip mode) 1 Bus right request output (BACK) (PB6 in single chip mode) 1 • Bits 11 and 10—PB5 Mode (PB5MD1 and PB5MD0): PB5MD1 and PB5MD0 select the function of the PB5/IRQ3/POE3/RDWR pin.
• Bits 5 and 4—PB2 Mode (PB2MD1 and PB2MD0): PB2MD1 and PB2MD0 select the function of the PB2/IRQ0/POE0/RAS pin. Bit 5: PB2MD1 Bit 4: PB2MD0 Description 0 0 General input/output (PB2) (initial value) 1 Interrupt request input (IRQ0) 0 Port output enable (POE0) 1 Row address strobe (RAS) (PB2 in single chip mode) 1 • Bit 3—Reserved: This bit always reads as 0. The write value should always be 0. • Bit 2—PB1 Mode (PB1MD): Selects the function of the PB1/A17 pin.
18.3.7 Port C I/O Register (PCIOR) The port C I/O register (PCIOR) is a 16-bit read/write register that selects input or output for the 16 port C pins. Bits PC15IOR–PC0IOR correspond to pins PC15/A15 to PC0/A0. PCIOR is enabled when the port C pins function as general input/outputs (PC15–PC0). For other functions, it is disabled. When the port C pin functions are as PC15–PC0, a given pin in port C is an output pin if its corresponding PCIOR bit is set to 1, and an input pin if the bit is cleared to 0.
18.3.8 Port C Control Register (PCCR) PCCR is a 16-bit read/write register that selects the functions for the sixteen port C multiplexed pins. There are instances when these register settings will be ignored, depending on the operation mode. Refer to table 18.2, Pin Arrangement by Mode, for details. PCCR is initialized to H'0000 by power-on resets but is not initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
• Bit 12—PC12 Mode (PC12MD): Selects the function of the PC12/A12 pin. Bit 12: PC12MD Description 0 General input/output (PC12) (initial value) (A12 in on-chip ROM invalid mode) 1 Address output (A12) (PC12 in single chip mode) • Bit 11—PC11 Mode (PC11MD): Selects the function of the PC11/A11 pin.
• Bit 6—PC6 Mode (PC6MD): Selects the function of the PC6/A6 pin. Bit 6: PC6MD Description 0 General input/output (PC6) (initial value) (A6 in on-chip ROM invalid mode) 1 Address output (A6) (PC6 in single chip mode) • Bit 5—PC5 Mode (PC5MD): Selects the function of the PC5/A5 pin. Bit 5: PC5MD Description 0 General input/output (PC5) (initial value) (A5 in on-chip ROM invalid mode) 1 Address output (A5) (PC5 in single chip mode) • Bit 4—PC4 Mode (PC4MD): Selects the function of the PC4/A4 pin.
• Bit 0—PC0 Mode (PC0MD): Selects the function of the PC0/A0 pin. Bit 0: PC0MD Description 0 General input/output (PC0) (initial value) (A0 in on-chip ROM invalid mode) 1 Address output (A0) (PC0 in single chip mode) 18.3.9 Port D I/O Register H (PDIORH) The port D I/O register H (PDIORH) is a 16-bit read/write register that selects input or output for the most significant sixteen port D pins. Bits PD31IOR–PD16IOR correspond to the PD31/D31/ADTRG pin to PD16/D16/IRQ0 pin.
18.3.10 Port D I/O Register L (PDIORL) The port D I/O register L (PDIORL) is a 16-bit read/write register that selects input or output for the least significant sixteen port D pins. Bits PD15IOR–PD0IOR correspond to the PD15/D15 pin to PD0/D0 pin. PDIORL is enabled when the port D pins function as general input/outputs (PD15–PD0). For other functions, it is disabled.
Port D Control Register H1 (PDCRH1): Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PD31 MD1 PD31 MD0 PD30 MD1 PD30 MD0 PD29 MD1 PD29 MD0 PD28 MD1 PD28 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PD27 MD1 PD27 MD0 PD26 MD1 PD26 MD0 PD25 MD1 PD25 MD0 PD24 MD1 PD24 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 and 14—PD31 Mode 1, 0 (PD31MD1 and PD31MD0): These bits select the fun
• Bits 11 and 10—PD29 Mode 1, 0 (PD29MD1 and PD29MD0): These bits select the function of the PD29/D29/CS3 pin.
• Bits 5 and 4—PD26 Mode 1, 0 (PD26MD1 and PD26MD0): These bits select the function of the PD26/D26/DACK0 pin.
Port D Control Register H2 (PDCRH2): Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PD23 MD1 PD23 MD0 PD22 MD1 PD22 MD0 PD21 MD1 PD21 MD0 PD20 MD1 PD20 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PD19 MD1 PD19 MD0 PD18 MD1 PD18 MD0 PD17 MD1 PD17 MD0 PD16 MD1 PD16 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 and 14—PD23 Mode 1, 0 (PD23MD1 and PD23MD0): These bits select the fun
• Bits 11 and 10—PD21 Mode 1, 0 (PD21MD1 and PD21MD0): These bits select the function of the PD21/D21/IRQ5 pin. Bit 11: PD21MD1 Bit 10: PD21MD0 0 0 General input/output (PD21) (initial value) (D21 with no ROM and CS0 = 32 bit width) 1 Data input/output (D21) (PD21 in single chip mode) 0 Interrupt request input (IRQ5) 1 Reserved 1 Description • Bits 9 and 8—PD20 Mode 1, 0 (PD20MD1 and PD20MD0): These bits select the function of the PD20/D20/IRQ4 pin.
• Bits 5 and 4—PD18 Mode 1, 0 (PD18MD1 and PD18MD0): These bits select the function of the PD18/D18/IRQ2 pin. Bit 5: PD18MD1 Bit 4: PD18MD0 0 0 General input/output (PD18) (initial value) (D18 with no ROM and CS0 = 32 bit width 1 Data input/output (D18) (PD18 in single chip mode) 0 Interrupt request input (IRQ2) 1 Reserved 1 Description • Bits 3 and 2—PD17 Mode 1, 0 (PD17MD1 and PD17MD0): These bits select the function of the PD17/D17/IRQ1 pin.
18.3.12 Port D Control Register L (PDCRL) PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least significant sixteen port D pins. There are instances when these register settings will be ignored, depending on the operation mode. On-Chip ROM-Disabled Extended Mode: • 144-pin version: Mode 0 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled. Mode 1 (32-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.
• Bit 15—PD15 Mode (PD15MD): Selects the function of the PD15/D15 pin. Bit 15: PD15MD Description 0 General input/output (PD15) (initial value) (D15 in on-chip ROM invalid mode) 1 Data input/output (D15) (PD15 in single chip mode) • Bit 14—PD14 Mode (PD14MD): Selects the function of the PD14/D14 pin.
• Bit 9—PD9 Mode (PD9MD): Selects the function of the PD9/D9 pin. Bit 9: PD9MD Description 0 General input/output (PD9) (initial value) (D9 in on-chip ROM invalid mode) 1 Data input/output (D9) (PD9 in single chip mode) • Bit 8—PD8 Mode (PD8MD): Selects the function of the PD8/D8 pin.
• Bit 3—PD3 Mode (PD3MD): Selects the function of the PD3/D3 pin. Bit 3: PD3MD Description 0 General input/output (PD3) (initial value) (D3 in on-chip ROM invalid mode) 1 Data input/output (D3) (PD3 in single chip mode) • Bit 2—PD2 Mode (PD2MD): Selects the function of the PD2/D2 pin.
18.3.13 Port E I/O Register (PEIOR) The port E I/O register (PEIOR) is a 16-bit read/write register that selects input or output for the 16 port E pins. Bits PE15IOR–PE0IOR correspond to pins PE15/TIOC4D/DACK1/IRQOUT– PE0/TIOC0A/DREQ0. PEIOR is enabled when the port E pins function as general input/outputs (PE15–PE0) or TIOC pin of the MTU. For other functions, it is disabled.
Port E Control Register 1 (PECR1): Bit: 15 14 13 12 11 10 9 8 PE15 MD1 PE15 MD0 PE14 MD1 PE14 MD0 PE13 MD1 PE13 MD0 — PE12MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W 7 6 5 4 3 2 1 0 — PE11MD — PE10MD — PE9MD — PE8MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Initial value: R/W: Bit: • Bits 15 and 14—PE15 Mode 1, 0 (PE15MD1 and PE15MD0): These bits select the function of the PE15/TIOC4D/DACK1/IRQOUT pin.
• Bits 11 and 10—PE13 Mode 1, 0 (PE13MD1 and PE13MD0): These bits select the function of the PE13/TIOC4B/MRES pin. Bit 11: PE13MD1 Bit 10: PE13MD0 Description 0 0 General input/output (PE13) (initial value) 1 MTU input capture input/output compare output (TIOC4B) 0 Manual reset input (MRES) 1 Reserved 1 • Bit 9—Reserved: This bit always reads as 0. The write values should always be 0. • Bit 8—PE12 Mode (PE12MD): Selects the function of the PE12/TIOC4A pin.
• Bit 2—PE9 Mode (PE9MD): Selects the function of the PE9/TIOC3B pin. Bit 2: PE9MD Description 0 General input/output (PE9) (initial value) 1 MTU input capture input/output compare output (TIOC3B) • Bit 1—Reserved: This bit always reads as 0. The write values should always be 0. • Bit 0—PE8 Mode (PE8MD): Selects the function of the PE8/TIOC3A pin.
• Bit 12—PE6 Mode (PE6MD): Selects the function of the PE6/TIOC2A pin. Bit 12: PE6MD Description 0 General input/output (PE6) (initial value) 1 MTU input capture input/output compare output (TIOC2A) • Bit 11—Reserved: This bit always reads as 0. The write value should always be 0. • Bit 10—PE5 Mode (PE5MD): Selects the function of the PE5/TIOC1B pin.
• Bits 5 and 4—PE2 Mode 1, 0 (PE2MD1 and PE2MD0): These bits select the function of the PE2/TIOC0C/DREQ1 pin. Bit 5: PE2MD1 Bit 4: PE2MD0 Description 0 0 General input/output (PE2) (initial value) 1 MTU input capture input/output compare output (TIOC0C) 0 DREQ1 request receive input (PE2 in single chip mode) 1 Reserved 1 • Bits 3 and 2—PE1 Mode 1, 0 (PE1MD1 and PE1MD0): These bits select the function of the PE1/TIOC0B/DRAK0 pin.
The IFCR is initialized to H'0000 by external power-on reset but is not initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
18.4 Cautions on Use For the I/O ports and pins with multiplexing of DREQ or IRQ, switching from the port input Low level condition to IRQ or DREQ edge detection will detect the concerned edge.
646
Section 19 I/O Ports (I/O) 19.1 Overview There are six ports, A, B, C, D, E, and F. The pins of the ports are multiplexed for use as generalpurpose I/Os (the port F pins are general input) or for other functions. Use the pin function controller (PFC) to select the function of multiplexed pins. The ports each have one data register for storing pin data. The initialize function after power-on reset differs depending on the operating mode of each pin. See table 18.2, Pin Arrangement by Mode, for details.
Table 19.
Table 19.
19.2.1 Register Configuration Table 19.3 summarizes the port A register. Table 19.3 Port A Register Name R/W Initial Value Address Access Size Port A data register H PADRH R/W H'0000 H'FFFF8380 H'FFFF8381 8, 16, 32 Port A data register L PADRL R/W H'0000 H'FFFF8382 H'FFFF8383 8, 16, 32 19.2.2 Abbreviation Port A Data Register H (PADRH) PADRH is a 16-bit read/write register that stores data for port A. The bits PA23DR–PA16DR correspond to the PA23/WRHH–PA16/AH pins.
19.2.3 Port A Data Register L (PADRL) PADRL is a 16-bit read/write register that stores data for port A. The bits PA15DR–PA0DR correspond to the PA15/CK–PA0/RXD0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PADRL; when PADRL is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADRL is read.
19.3 Port B Port B is a 10-pin input/output port as listed in table 19.5. Table 19.
19.3.2 Port B Data Register (PBDR) PBDR is a 16-bit read/write register that stores data for port B. The bits PB9DR–PB0DR correspond to the PB9/IRQ7/A21/ADTRG–PB0/A16 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PBDR is read.
19.4 Port C Port C is a 16 pin input/output port as listed in table 19.8. Table 19.
19.4.2 Port C Data Register (PCDR) PCDR is a 16-bit read/write register that stores data for port C. The bits PC15DR–PC0DR correspond to the PC15/A15–PC0/A0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PCDR; when PCDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PCDR is read.
19.5 Port D There are two versions of port D: • FP-112 • FP-144 In the FP-112 version, port D is a 16-pin input/output port, as shown in table 19.11. Table 19.
Table 19.
Table 19.
19.5.2 Port D Data Register H (PDDRH) PDDRH is a 16-bit read/write register that stores data for port D. The bits PD31DR–PD16DR correspond to the PD31/D31/ADTRG–PD16/D16/IRQ0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PDDRH; when PDDRH is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PDDRH is read.
19.5.3 Port D Data Register L (PDDRL) PDDRL is a 16-bit read/write register that stores data for port D. The bits PD15DR–PD0DR correspond to the PD15/D15–PD0/D0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PDDRL; when PDDRL is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PDDRL is read.
19.6 Port E Port E is a 16-pin input/output port, as listed in table 19.15. Table 19.
19.6.2 Port E Data Register (PEDR) PEDR is a 16-bit read/write register that stores data for port E. The bits PE15DR–PE0DR correspond to the PE15/TIOC4D/DACK1/IRQOUT–PE0/TIOC0A/DREQ0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PEDR; when PEDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PEDR is read.
19.7 Port F Port F is an 8-pin input port. All modes are configured in the following way: • • • • • • • • PF7 (input)/AN7 (input) PF6 (input)/AN6 (input) PF5 (input)/AN5 (input) PF4 (input)/AN4 (input) PF3 (input)/AN3 (input) PF2 (input)/AN2 (input) PF1 (input)/AN1 (input) PF0 (input)/AN0 (input) 19.7.1 Register Configuration Table 19.18 summarizes the port F register. Table 19.
Table 19.
Section 20 64/128/256kB Mask ROM 20.1 Overview This LSI is available with 64 kbytes, 128 kbytes, or 256 kbytes of on-chip ROM. The on-chip ROM is connected to the CPU, direct memory access controller (DMAC) and data transfer controller (DTC) through a 32-bit data bus (figures 20.1, 20.2, and 20.3). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits) H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 On-chip ROM H'0001FFFC H'0001FFFD H'0001FFFE H'0001FFFF Figure 20.2 Mask ROM Block Diagram (128-kbyte Version) Internal data bus (32 bits) H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 On-chip ROM H'0003FFFC H'0003FFFD H'0003FFFE H'0003FFFF Figure 20.
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD3–MD0 as shown in table 20.1. If you are using the on-chip ROM, select mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses H'00000000–H'0000FFFF of memory area 0 for the 64-kbyte version, H'00000000– H'0001FFFF of memory area 0 for the 128-kbyte version and H'00000000–H'0003FFFF of memory area 0 for the 256-kbyte version. Table 20.
668
Section 21 128kB PROM 21.1 Overview This LSI has 128 kbytes of on-chip PROM.The on-chip ROM is connected to the CPU, the direct memory access controller (DMAC) and the data transfer controller (DTC) through a 32-bit data bus (figures 21.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Table 21.
EPROM socket HN27C101 SH7042 (112-pin version) adapter Pin number Pin name Pin name Pin number 0.
SH7042 (120-pin version) Pin number EPROM socket adapter Pin name 0.
SH7043 (144-pin version) Pin number 108 98 92 91 90 89 88 86 84 83 7 8 9 10 11 13 15 16 17 32 19 20 21 22 23 24 25 34 5 2 36 12, 26, 40, 63, 77, 85, 99, 112, 135 103 102 97 104, 128, 127 105, 106, 96 6, 14, 28, 35, 42, 55, 61, 71, 79, 87, 93, 117, 129, 141 118–123, 125, 126 124 95 EPROM socket HN27C101 adapter Pin name Pin name Pin number 0.
Address for MCU modes 0, 1, 2, 3 Address for PROM mode H'00000000 H'0000 On-chip ROM space (area 0) H'0001FFFF (128-kbyte version) H'1FFFF (128-kbyte version) Figure 21.5 On-Chip ROM Memory Map 21.3 PROM Programming The PROM mode write/verify specifications are the same as those of the standard EPROM HN27C101. However, because the page program format is not supported, do not set the PROM writer to the page programming mode. PROM writers that only support page programming mode cannot be used.
21.3.2 Write/Verify and Electrical Characteristics Write/Verify: Writing and verification can be done using an efficient high speed, high reliability programming format. This format allows data writing that is both fast and reliable without applying voltage stress to the device. Figure 21.6 shows the basic flow of the high speed, high reliability programming format.
< Preliminary > Start Set EPROM writer to write/verify mode (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V) Address = 0 n=0 n+1→n No Yes Data write (tPW = 0.2 ms ± 5%) n = 25? No Address + 1 → address Is verify result OK? Yes Data write (tOPW = 0.2n ms) Final address? No Yes Set EPROM writer to read mode (VCC = 5.0 V ± 0.
Electrical Characteristics: Tables 21.3 and 21.4 show the electrical characteristics for programming. Figure 21.7 shows the timing. Table 21.3 DC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C) Item Pin Symbol Min Typ Max Input high-level voltage I/O7–I/O0, A16–A0, OE, CE, PGM VIH 2.
Table 21.4 AC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C) Typ Max Unit Measurement Conditions 2 — — µs Figure 21.6 * 1 t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs Data output disable time t DF*2 — — 130 ns Vpp setup time t VPS 2 — — µs Item Symbol Min Address setup time t AS OE setup time PGM pulse width during initial programming t PW 0.19 0.20 0.
Write Verify Address tAS tAH Write data Data VCC tDF tDH tDS VPP Read data VPP VCC tVPS VCC + 1 VCC tVCS CE tCES PGM tPW tOES tOE (tOPW)* OE Note: * tOPW is defined by the values noted in the flowchart (figure 19.6). Figure 21.7 Write/Verify Timing 21.3.3 Cautions on Writing 1. Writes must always be done with the established voltage and timing. The write voltage (programming voltage) VPP is 12.5 V (when the EPROM writer is set for the HN27C101 Hitachi specifications, VPP becomes 12.5 V).
5. Terminate the writing if a write malfunction occurs in consecutive addresses. In such cases, check for problems in the EPROM writer and/or socket adapter. There are some cases where write/verify will not be possible if using an EPROM writer with a high impedance power supply system. 6. Use a EPROM writer that conforms to the socket adapter supported by this LSI. 21.3.
Section 22 256kB Flash Memory (F-ZTAT) 22.1 Features This LSI has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Block erase (in single-block units) can be performed. Block erasing can be performed as required on 1 kbyte, 28 kbyte, and 32 kbyte blocks.
22.2 Overview 22.2.1 Block Diagram Internal address bus Module bus Internal data bus (32-bit) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operation mode EBR2 RAMER Flash memory (256kB) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1 : Block specification register 1 EBR2 : Block specification register 2 RAMER : RAM emulation register Figure 22.
22.2.2 Mode Transition Diagram When the mode pins and the FWP pin are set in the reset state and a reset start is executed, the microcomputer enters one of the operating modes shown in figure 22.2. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode.
22.2.3 Onboard Program Mode Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
User program mode 1. Initial state The FWP assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2.
22.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. • User Mode • User Program Mode SCI Flash memory RAM Application program Overlap RAM (Emulation is executed using data written to RAM) Emulation block Figure 22.
• User Program Mode SCI Flash memory RAM Programming control program execution state Application program Overlap RAM (Programming data) Programming data Figure 22.6 Programming to the Flash Memory 22.2.5 Differences between Boot Mode and User Program Mode Table 22.
22.2.6 Block Configuration The flash memory is divided into seven 32 kbyte blocks, one 28 kbyte blocks, and four 1 kbyte blocks. Address H'00000 32kbyte 32kbyte 32kbyte 256kbyte 32kbyte 32kbyte 32kbyte 32kbyte 28kbyte Address H'3FFFF 1kbyte 1kbyte 1kbyte 1kbyte Figure 22.
22.3 Pin Configuration The flash memory is controlled by the pins shown in table 22.2. Table 22.
22.5 Description of Registers 22.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000–H'1FFFF is entered by setting SWE to 1 when FWE = 1, then setting the EV1 or PV1 bit. Program mode for addresses H'00000–H'1FFFF is entered by setting SWE to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit.
Bit 5: ESU1 Description 0 Erase setup release (Initial value) 1 Erase setup [Setting condition] When FWE=1 and SWE=1 • Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode (applicable addresses: H'00000–H'1FFFFF). Do not set the SWE, ESU1, EV1, PV1, E1, or P1 bit at the same time.
• Bit 1—Erase 1 (E1): Selects erase mode transition or release (applicable addresses: H'00000– H'1FFFF). Do not set the SWE, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1: E1 Description 0 Erase mode release (Initial value) 1 Transition to erase mode [Setting condition] When FWE=1, SWE=1, and ESU1=1 • Bit 0—Program 1 (P1): Selects program mode transition or release (applicable addresses: H'00000–H'1FFFF). Do not set the SWE, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Bit: 7 6 5 4 3 2 1 0 FLER — ESU2 PSU2 EV2 PV2 E2 P2 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W • Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7: FLER Description 0 Flash memory is operating normally.
• Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or release (applicable addresses: H'20000–H'3FFFF). Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3: EV2 Description 0 Erase verify mode release (Initial value) 1 Transition to the erase verify mode [Setting condition] When FWE=1 and SWE=1 • Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or release (applicable addresses: H'20000–H'3FFFF).
22.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset and standby mode, when a high level is input to the FWP pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit.
Table 22.4 Flash Memory Erase Blocks Block (size) Addresses EB0 (32kB) H'000000–H'007FFF EB1 (32kB) H'008000–H'00FFFF EB2 (32kB) H'010000–H'017FFF EB3 (32kB) H'018000–H'01FFFF EB4 (32kB) H'020000–H'027FFF EB5 (32kB) H'028000–H'02FFFF EB6 (32kB) H'030000–H'037FFF EB7 (28kB) H'038000–H'03EFFF EB8 (1kB) H'03F000–H'03F3FF EB9 (1kB) H'03F400–H'03F7FF EB10 (1kB) H'03F800–H'03FBFF EB11 (1kB) H'03FC00–H'03FFFF 22.5.
• Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. This bit is ignored when the on-chip ROM is disabled.
22.6 On-Board Programming Mode When pins are set to on-board programming mode and a power-on reset is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 22.6. For a diagram of the transitions to the various flash memory modes, see figure 22.2. Table 22.
22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI to be used is set to channel asynchronous mode. When a reset start is executed after the LSI pins have been set to boot mode in the power-on reset state, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via SCI channel 1.
Start Set pin to the boot program mode then reset start The host continuously sends data (H'00) using a fixed bit rate This LSI measures the low period of data H'00 sent by the host This LSI calculates the bit rate and sets value to the bit rate register After adjustment of the bit rate, this LSI sends 1 byte of data H'00 to the host as a sign of completion of adjustment The host checks whether the sign (H'00) indicating completion of bit rate adjustment is received, then transmits 1 byte of data H'55 Afte
Automatic SCI Bit Rate Adjustment Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop Bit High period of more than 1 bit Figure 22.10 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 22.11. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFFFF000 Programming control program area (2k bytes) H'FFFFF800 Boot program area (2k bytes) H'FFFFFFFF Figure 22.
22.6.2 User Program Mode After setting FWP, the user should branch to, and execute, the previously prepared programming/erase control program. As the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip RAM or external memory. Use the following procedure (figure 22.12) to execute the programming control program that writes to flash memory (when transferred to RAM).
22.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'00000–H'1FFFF, or the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2 for addresses H'20000–H'3FFFF.
FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set 200 µs as the time for one programming operation. 22.7.2 Program-Verify Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000–H'3FFFF) In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Start Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
• Sample 32-byte programming program The wait time set values (number of loops) are for the case where f = 28.7 MHz. For other frequencies, the set value is given by the following expression: Wait time (µs) × f (MHz) ÷ 4 Registers Used R4 (input): R5 (input): R7 (output): R0-3, 8-13: Program data storage address Programming destination address OK (normal) or NG (error) Work registers FLMCR1 .EQU H’80 FLMCR2 .EQU H’81 OK .EQU H’0 NG .EQU H’1 Wait10u .EQU 72 Wait50u .EQU 359 Wait4u .
MOV.L @R12+,R1 MOV.L R1,@R0 ADD.L #4,R0 ADD.L #-1,R13 CMP/PL R13 BT COPY_LOOP MOV.L #H’FFFF8500,R0 LDC R0,GBR MOV.L #Wait10u,R3 MOV.L #FLMCR1,R0 ; Initialize R0 to FLCMR1 address OR.B #SWESET,@(R0,GBR) ; Set SWE SUBC R2,R3 ; Wait 10 µs BF Wait_1 MOV.L #H’20000,R9 CMP/GT R5,R9 ; Initialize GBR ; Wait_1 ; BT Program_Start MOV.L #FLMCR2,R0 Program_Start MOV.L .EQU $ ; Initialize n (R9) to 0 #0,R9 ; Program_loop .EQU $ MOV.
MOV.W R3,@R1 MOV.L #Wait50u,R3 OR.B #PSU1SET,@(R0,GBR) ; Set PSU SUBC R2,R3 ; Wait 50 µs ; Wait_2 BF ; Wait_3 MOV.L #Wait200u,R3 OR.B #P1SET,@(R0,GBR) ; Set P SUBC R2,R3 ; Wait 200 µs BF Wait_3 MOV.L #Wait10u,R3 ; Wait_4 AND.B #P1CLEAR,@(R0,GBR) ; Clear P SUBC R2,R3 ; Wait 10 µs BF Wait_4 MOV.L #Wait10u,R3 AND.B #PSU1CLEAR,@(R0,GBR) ; Clear PSU SUBC R2,R3 ; Wait 10 µs BF Wait_5 MOV.L #WDT_TCSR,R1 MOV.W #H’A55F,R3 MOV.W R3,@R1 MOV.L #Wait4u,R3 OR.
VerifyLoop Wait_7 .EQU $ MOV.L R11,@R12 ; Write H'FF to verify address MOV.L R11,@R3 ; Reprogram data RAM (PdataBuff) initialization MOV.L #Wait2u,R7 SUBC R2,R7 BF Wait_7 MOV.L @R12+,R7 MOV.L @R1+,R8 CMP/EQ R7,R8 BT Verify_OK MOV.L #1,R10 ; Verify NG, m <- 1 XOR R8,R7 ; Program data computation NOT R7,R7 OR R7,R8 MOV.L R8,@R3 ; Wait 2 µs ; Verify_OK .EQU ; Verify ; Store in reprogram data RAM (PdataBuff) $ ADD.L #4,R3 ADD.
MOV.L Program_end ; R7 <- OK (return value) #OK,R7 .EQU $ MOV.B #H’00,R0 MOV.B R0,@(FLMCR1,GBR) ; Clear SWE ; RTS NOP ; .ALIGN PdataBuff 22.7.3 4 .RES.B 32 Erase Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000– H'3FFFF) When erasing flash memory, the erase/erase-verify flowchart shown in figure 22.14 should be followed.
22.7.4 Erase-Verify Mode (n = 1 for Addresses H'00000–H'1FFFF, n = 2 for Addresses H'20000–H'3FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
Start *1 Set SWE bit in FLMCR1 Wait 10 µs *5 n=1 *3 Set EBR1(2) Enable WDT Set ESU1(2) bit in FLMCR1(2) Wait 200 µs *5 Start erase Set E1(2) bit in FLMCR1(2) Wait 5 ms *5 Clear E1(2) bit in FLMCR1(2) Halt erase Wait 10 µs *5 Clear ESU1(2) bit in FLMCR1(2) Wait 10 µs *5 Disable WDT n←n+1 Set EV1(2) bit in FLMCR1(2) Wait 20 µs *5 Set block start address to verify address H'FF dummy write to verify address Increment address Wait 2 µs *5 Read verify data *2 Verify data = all "1"? NG O
• Sample one-block erase program The wait time set values (number of loops) are for the case where f = 28.7 MHz. For other frequencies, the set value is given by the following expression: Wait time (µS) × f (MHz) ÷ 4 The WDT overflow cycle set value is for the case where f = 28.7 MHz. For other frequencies, ensure that the overflow cycle is a minimum of 5.3 ms. Registers Used R5 (input): R7 (output): R0-3, 6, 8-9: Memory block table pointer OK (normal) or NG (error) Work registers FLMCR1 .
; MOV.L #Wait10u,R3 MOV.L #FLMCR1,R0 OR.B #SWESET,@(R0,GBR) ; Set SWE R2,R3 ; Wait 10 µs EWait_1 SUBC BF EWait_1 MOV.L #0,R9 MOV.B @(6,R5),R0 MOV.B R0,@(EBR1,GBR) MOV.B @(7,R5),R0 MOV.B R0,@(EBR2,GBR) MOV.L #FLMCR1,R0 MOV.L @R5,R6 MOV.L #H’020000,R7 CMP/GT R6,R7 BT EraseLoop MOV.L #FLMCR2,R0 ; ; Initialize n (R9) to 0 ; ; Erase memory block (EBR1) setting ; Erase memory block (EBR2) setting ; ; Erase memory block start address -> R6 ; EraseLoop .EQU $ MOV.
AND.B EWait_4 SUBC #ECLEAR,@(R0,GBR) ; Clear E R2,R3 ; Wait 10 µs BF EWait_4 MOV.L #Wait10u,R3 ; AND.B EWait_5 SUBC BF #ESUCLEAR,@(R0,GBR) ; Clear ESU R2,R3 ; Wait 10 µs EWait_5 ; ; Disable WDT MOV.L #WDT_TCSR,R1 MOV.W #H’A55F,R3 MOV.W R3,@R1 MOV.L #Wait20u,R3 OR.B #EVSET,@(R0,GBR) ; Set EV R2,R3 ; Wait 20 µs ; EWait_6 SUBC BF EWait_6 MOV.L @R5,R6 ; BlockVerify_1 .EQU ; Erase memory block start address -> R6 $ MOV.L #H’FFFFFFFF,R8 MOV.L R8,@R6 MOV.
MOV.L #OK,R7 ; R7 <- OK (return value) BRA FlashErase_end ; Verify OK NOP ; BlockVerify_NG .EQU $ ; Verify NG, n <- n + 1 ADD.L #1,R9 MOV.L #Wait5u,R3 AND.B #EVCLEAR,@(R0,GBR) ; Clear EV R2,R3 ; Wait 5 µs EWait_9 SUBC BF EWait_9 MOV.L #MAXErase,R7 CMP/EQ R7,R9 BF EraseLoop MOV.L #NG,R7 FlashErase_end .EQU ; If n > MAXErase then erase NG ; R7 <- NG (return value) $ MOV.L #FLMCR1,R0 AND.B #SWECLEAR,@(R0,GBR) ; Clear SWE ; RTS NOP ; ; Memory block table .
22.8 Protection There are two kinds of flash memory program/erase protection, hardware protection and software protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2).
22.8.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2 bit in flash memory control register 2 (FLMCR2), does not cause a transition to program mode or erase mode. (See table 22.9.
22.8.3 Error Protection In error protection, an error is detected when microcomputer runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Program mode Erase mode Reset or standby (hardware protection) RES = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Er ro r( sta nd by ) RE S =0 Error RES = 0 Error protection mode RD VF PR ER FLER = 0 Standby mode Software standby mode release Legend RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erase enable RD: VF: PR: ER: FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, EBR1, E
22.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 22.16 shows an example of emulation of real-time flash memory programming.
H'000000 Flash memory EB0 to 7 This area can be accessed from both RAM and flash memory H'03F000 EB8 H'03F400 EB9 H'03F800 EB10 H'03FC00 H'03FFFF EB11 On-chip RAM H'FFFFF800 H'FFFFFBFF Figure 22.17 Example of RAM Overlap Operation Example in which Flash Memory Block Area (EB8) is Overlapped 1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 1, to overlap part of RAM onto the area (EB8) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3.
22.10 Note on Flash Memory Programming/Erasing In the on-board programming modes (user mode and user program mode), NMI input should be disabled to give top priority to the program/erase operations (including RAM emulation). 22.11 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported.
22.11.1 Socket Adapter Pin Correspondence Diagrams Connect the socket adapter to the chip as shown in figures 22.19 and 22.20. This will enable conversion to a 32-pin arrangement. The on-chip ROM memory map is shown in figure 22.18, and socket adapter pin correspondence diagrams in figures 22.19 and 22.20. Addresses in MCU mode Addresses in writer mode H'00000000 H'00000 On-chip ROM space 256 kB H'0003FFFF H'3FFFF Figure 22.
HD64F7044 (112-Pin) Pin Name Pin No.
HD64F7045 (144-Pin) Pin Name Pin No.
22.11.2 Programmer Mode Operation Table 22.11 shows how the different operating modes are set when using programmer mode, and table 22.12 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory.
Table 22.12 Commands of the Programmer Mode First Cycle Command Name Number of Cycles Mode Second Cycle Address Data Mode Address Data Memory read mode 1+n write X H'00 read RA Dout Auto-program mode 129 write X H'40 write WA Din Auto-erase mode 2 write X H'20 write X H'20 Status read mode 2 write X H'71 write X H'71 Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2.
Command write Memory read mode Address stable A16-0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7-0 Note: Data is latched on the rising edge of WE. Figure 22.21 Timing Waveforms for Memory Read after Memory Write Table 22.14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 5.
Memory read mode A16-0 Other mode command write Address stable tnxtc tces tceh CE OE twep tf tr WE tds tdh I/O7-0 Note: Do not enable WE and OE at the same time. Figure 22.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 22.15 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.
Address stable A16-0 CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7-0 Figure 22.23 CE and OE Enable State Read Timing Waveforms Address stable A16-0 Address stable tce tce CE toe toe OE WE VIH tacc tacc toh tdf toh I/O7-0 Figure 22.
22.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 8 bits of the transfer address must be H'00 or H'80.
Table 22.16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 5.
22.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing.. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status output uses the auto-erase operation end identification pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write.
;;;; FWE tenh A16-0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds terase tdh I/O7 Erase complete verify signal I/O6 I/O5-0 Erase normal complete verify signal H'20 H'20 H'00 Figure 22.26 Auto-Erase Mode Timing Waveforms 22.11.6 Status Read Mode Table 22.18 AC Characteristics in Status Read Mode (Conditions: VCC = 5.
;;;; A16-0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE twep tf tr twep tf tr toe WE tds tdh I/O7-0 tds H'71 tdf tdh H'71 Note : I/O2 and I/O3 are undefined. Figure 22.27 Status Read Mode Timing Waveforms Table 22.
Table 22.20 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O5–0 0 0 0 0 Normal End 22.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 22.
22.11.9 Cautions Concerning Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology.
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Section 23 RAM 23.1 Overview The SH7040 series has 4 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC)/data transfer controller (DTC) with a 32-bit data bus (figure 23.1). The CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The DMAC can access 8 or 16 bit widths. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access.
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Section 24 Power-Down State 24.1 Overview In the power-down state, the CPU functions are halted. This enables a great reduction in power consumption. 24.1.1 Power-Down States The power-down state is effected by the following two modes: • Sleep mode • Standby mode Table 24.1 describes the transition conditions for entering the modes from the program execution state as well as the CPU and peripheral function status in each mode and the procedures for canceling each mode. Table 24.
24.1.2 Related Register Table 24.2 shows the register used for power-down state control. Table 24.2 Related Register Name Abbreviation R/W Initial Value Address Access Size Standby control register SBYCR R/W H'1F H'FFFF8614 8, 16, 32 24.2 Standby Control Register (SBYCR) The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to standby mode, and the port status in standby mode. The SBYCR is initialized to H'1F when reset.
24.3 Sleep Mode 24.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the program execution state to the sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run during the sleep mode. 24.3.
Table 24.
Table 24.3 Register States in the Standby Mode (cont) Module Registers Initialized Registers that Retain Data Registers with Undefined Contents Pin function controller (PFC) — All registers — I/O port (I/O) — All registers — Power-down state related — Standby control — register (SBYCR) 24.4.2 Canceling the Standby Mode The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset.
24.4.3 Standby Mode Application Example This example describes a transition to standby mode on the falling edge of an NMI signal, and a cancellation on the rising edge of the NMI signal. The timing is shown in figure 24.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) of the ICR is set to 0 (falling edge detection), the NMI interrupt is accepted.
Section 25 Electrical Characteristics (5V, 28.7 MHz Version) 25.1 Absolute Maximum Ratings Table 25.1 shows the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC –0.3 to +7.0 V Programmable voltage (ZTAT version only) VPP –0.3 to +13.5 V Input voltage (other than A/D ports) Vin –0.3 to VCC + 0.3 V Input voltage (A/D ports) Vin –0.3 to AVCC + 0.3 V Analog supply voltage AVCC –0.3 to +7.
25.2 DC Characteristics Table 25.2 DC Characteristics (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = –20 to +75° C) Item Max Measurement Unit Conditions VCC – 0.7 — VCC + 0.3 V — EXTAL VCC × 0.7 — VCC + 0.3 V — A/D port 2.2 — AVCC + 0.3 V — Other input pins 2.2 — VCC + 0.3 V — RES, NMI, MD3– VIL MD0, PA2, PA5, PA6–PA9, PE0– PE15, FWP –0.3 — 0.5 V — –0.3 — 0.8 V — — — V VT + ≥ VCC – 0.
Table 25.2 DC Characteristics (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = –20 to +75°C) (cont) Item Pin Symbol Min Output high-level voltage All output pins VOH Typ Max Measurement Unit Conditions VCC – 0.5 — — V I OH = –200 µA 3.5 — — V I OH = –1 mA — — 0.4 V I OL = 1.6 mA — — 1.
Table 25.3 Permitted Output Current Values (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = –20 to +75° C) Item Symbol Min Typ Max Unit Output low-level permissible current (per pin) I OL — — 2.0 * mA Output low-level permissible current (total) ∑ IOL — — 80 mA Output high-level permissible current (per pin) –I OH — — 2.
tcyc tCL tCH CK 1/2VCC 1/2VCC tCF tCR Figure 25.1 System Clock Timing tEXcyc tEXH EXTAL 1/2VCC VIH tEXL VIH VIL VIL tEXF VIH 1/2VCC tEXR Figure 25.2 EXTAL Clock Input Timing CK VCC VCC min tOSC2 tOSC1 RES Figure 25.
25.3.2 Control Signal Timing Table 25.5 Control Signal Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = –20 to +75° C) Item Symbol Min Max Unit Figure RES rise/fall t RESr, t RESf — 200 ns 25.4 RES pulse width t RESW 20 — t cyc MRES pulse width t MRESW 20 — t cyc NMI rise/fall t NMIr, t NMIf — 200 ns 25.5 RES setup time* t RESS 35 — ns MRES setup time* t MRESS 35 — ns 25.4, 25.
CK tRESf tRESr tRESS tRESS VIH RES VIH VIL VIL tRESW tMRESS tMRESS VIH MRES VIL VIL tMRESW Figure 25.4 Reset Input Timing CK tNMIH tNMIr,tNMIf tNMIS VIH NMI VIL tIRQEH IRQ edge tIRQES VIH VIL tIRQLS IRQ level Figure 25.
CK tIRQOD tIRQOD IRQOUT Figure 25.6 Interrupt Signal Output Timing CK tBRQS tBRQS BREQ (Input) tBACKD1 BACK (Output) RD, RDWR, RAS, CASxx, CSn, WRxx tBZD tBZD A21–A0, D31–D0 Note: During the bus-release period of a self-refresh, RAS, CASx, and RDWR are output. Figure 25.
25.3.3 Bus Timing Table 25.6 Bus Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.
Table 25.7 Bus Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure Write address setup time t AS 0 — ns 25.8–25.9 Write address hold time t WR 5 — ns 25.8, 25.9, 25.
T1 T2 CK tAD A21–A0 tCSD1 tCSD2 CSn tRSD1 tOE tRSD2 RD (During read) tRDS tACC tRDH D31–D0 (During read) tWSD1 tWSD2 tWR WRxx (During write) tWRH tAS tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CSn, and RD. Figure 25.
T1 Tw T2 CK tAD A21–A0 tCSD1 tCSD2 CSn tRSD1 tRSD2 tOE RD (During read) tACC tRDH tRDS D31–D0 (During read) tWSD1 tWSD2 tWR WRxx (During write) tAS tWRH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CSn, and RD. Figure 25.
T1 Tw Tw Two T2 CK A21–A0 CSn RD (During read) D31–D0 (During read) WRxx (During write) D31–D0 (During write) tWTS tWTH tWTS tWTH WAIT DACKn Figure 25.
Tp Tr Tc1 Tc2 CK tAD tAD Column address Row address A21–A0 tRASD1 tASR tRAH tRASD2 RAS tRP tCASD1 tCASD2 CASxx (During read) RDWR tCAC (During read) tRDS tAA tRDH tRAC D31– D0 (During read) tCASD1 CASxx (During write) tCASD2 tRWD1 tRWD2 RDWR (During write) tDS tDH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn tRSD1 tRSD2 RD (During read) tWSD1 tWSD2 WRxx (During write) Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. Figure 25.
Tp Tr CK Tc1 Column address Row address tRASD1 tASR Tc2 tAD tAD A21–A0 RAS Tcw1 tRAH tRASD2 tRP tCASD1 tCASD2 CASxx (During read) RDWR (During read) tCAC tRDS tAA tRDH tRAC D31–D0 (During read) tCASD2 tCASD1 CASxx (During write) tRWD1 RDWR (During write) tRWD2 tDS tDH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn tRSD1 tRSD2 RD (During read) WRxx (During write) tWSD1 tWSD2 Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. Figure 25.
Tp Tpw Tr CK Trw Tc1 tAD Tcw1 Tc2 tAD Row address A21–A0 tRASD1 Column address tRASD2 tRAH tASR RAS Tcw2 tRP tCASD2 tCASD1 CASxx (During read) RDWR (During read) tCAC tRDS tAA tRDH tRAC D31–D0 (During read) tCASD1 CASxx (During write) tCASD2 tRWD1 tRWD2 RDWR (During write) tDS tWDD D31–D0 (During write) tDH tWDH tDACKD1 tDACKD1 DACKn tRSD1 RD (During read) tRSD2 tWSD1 tWSD2 WRxx (During write) Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and
Tp Tr Tc1 Tcw1 Tcw2 Tcwo Tc2 CK tAD A21–A0 tASR RAS tAD Row address tRASD1 Column address tRAH tRASD2 tRP tCASD2 tCASD1 CASxx (During read) RDWR (During read) tCAC tAA tRAC D31–D0 (During read) tRDS tCASD2 tCASD1 CASxx (During write) tRWD1 RDWR (During write) tRDH tRWD2 tDS tDH tWDD tWDH D31–D0 (During write) tWTS tWTH tWTS tWTH WAIT tDACKD1 tDACKD1 DACKn tRSD1 RD (During read) tWSD1 tRSD2 tWSD2 WRxx (During write) Note: tRDH is specified from fastest negate timing
Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD tAD Column address Row address A21–A0 tRASD1 tASR RAS Column address tRAH tRASD2 tRP tCASD1 tCASD2 CASxx (During read) tCASD1 tCASD2 tCP RDWR (During read) tCAC tAA tRDS tCASD1 CASxx (During write) tRDH tRDH tRAC D31–D0 (During read) tCAC tAA tRDS tCASD2 tCASD1 tCASD2 tCP tRWD1 tRWD2 tRWD1 tRWD2 RDWR (During write) tDS tDH tDS tWDD D31–D0 (During write) tWDH tDACKD1 tDH tWDD tWDH tDACKD1 tDACKD1 DACKn tRSD2 tRSD1 RD (During
TRp TRr1 TRr2 TRc TRcc CK tRASD1 tRASD2 RAS tCSR tCASD1 tCASD2 CASxx RDWR Figure 25.18 Self Refresh Ta1 CK Ta2 Ta3 Ta4 T1 TW TWo T2 tAD A21–A0 tCSD1 tCSD2 CS3 tAHD1 tAHD2 AH tRSD1 RD (During read) tMAD D15–D0 (During read) tRSD2 tMAH tRDS tRDH Address tWSD1 tWSD2 WRxx (During write) tWR tMAD D15–D0 (During write) tMAH tWDD tWDH Address tWTS tWTH tWTS tWTH tWRH WAIT tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CS3, and RD.
25.3.4 Direct Memory Access Controller Timing Table 25.8 Direct Memory Access Controller Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure DREQ0 and DREQ1 setup time t DRQS 18 — ns 25.20 DREQ0 and DREQ1 hold time t DRQH 18 — ns DREQ0 and DREQ1 pulse width t DRQW 1.5 — t cyc 25.21 DRAK output delay time — 18 ns 25.
CK DREQ0 DREQ1 Edge tDRQW Figure 25.21 DREQ0 and DREQ1 Input Timing (2) CK tDRAKD tDRAKD DRAKn Figure 25.
25.3.5 Multifunction Timer Pulse Unit Timing Table 25.9 Multifunction Timer Pulse Unit Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure Output compare output delay time t TOCD — 100 ns 25.23 Input capture input setup time t TICS 30 — ns Timer input setup time t TCKS 35 — ns Timer clock pulse width (single edge specification) t TCKWH/L 1.
25.3.6 I/O Port Timing Table 25.10 I/O Port Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure Port output data delay time t PWD — 100 ns 25.25 Port input hold time t PRH 35 — ns Port input setup time t PRS 35 — ns T1 T2 CK tPRS tPRH Port (Read) tPWD Port (Write) Figure 25.
25.3.7 Watchdog Timer Timing Table 25.11 Watchdog Timer Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure WDTOVF delay time t WOVD — 100 ns 25.26 CK tWOVD tWOVD WDTOVF Figure 25.
25.3.8 Serial Communication Interface Timing Table 25.12 Serial Communication Interface Timing (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Max Unit Figure Input clock cycle t scyc 4 — t cyc 25.27 Input clock cycle (clock sync) t scyc 6 — t cyc Input clock pulse width t sckw 0.4 0.6 t scyc Input clock rise time t sckr — 1.5 t cyc Input clock fall time t sckf — 1.
25.3.9 High-speed A/D Converter Timing (excluding A mask) Table 25.13 High-speed A/D Converter Timing (Conditions: V CC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) Item Symbol Min Typ Max Unit Figure External trigger input pulse width t TRGW 2 — — t cyc 25.29 External trigger input start delay time t TRGS 50 — — ns A/D conversion start delay time CKS = 0 tD 1.5 1.5 1.5 t cyc 1.5 1.5 1.
φ Address Write signal ADST Sampling timing ADF tD tSPL tCP tCONV tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time tCP : Operation time Figure 25.
25.3.10 Mid-speed Converter Timing (A mask) Table 25.14 shows Mid-speed converter timing Table 25.14 Mid-speed Converter Timing (Conditions:Vcc=5.0V ± 10%, AVcc=5.0V ± 10%, AVcc=Vcc ± 10%, AVref=4.5V to Avcc, Vss=AVss=0V, Ta=-20 to ± 75°C) Item Symbol Min Typ Max Unit Figure External trigger input pulse width t TRGW 2 — — t cyc 25.
(1) CK (2) Address Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1) (2) tD t SPL t CONV : ADCSR write cycle : ADCSR address : A/D conversion start delay time : Input sampling time : A/D conversion time Figure 25.
25.3.11 Measuring Conditions for AC Characteristics • Input reference levels: High level: 2.2 V Low level: 0.8 V • Output reference levels: High level: 2.0 V Low level: 0.
25.4 A/D Converter Characteristics Table 25.15 A/D Converter Timing (excluding A mask) (Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ± 10%, AVref = 4.5 V to AVCC , VSS = AVSS = 0 V, Ta = – 20 to +75°C) 28.7 MHz Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time (when CKS = 1) — — 2.
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Section 26 Electrical Characteristics (3.3V, 16.7 MHz Version) 26.1 Absolute Maximum Ratings Table 26.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC –0.3 to +7.0 V Programmable voltage (ZTAT version only) VPP –0.3 to +13.5 V Input voltage (other than A/D ports) Vin –0.3 to VCC + 0.3 V Input voltage (A/D ports) Vin –0.3 to AVCC + 0.3 V Analog supply voltage AVCC –0.3 to +7.0 V Analog reference voltage (QFP-144 only) AVref –0.3 to AVCC + 0.
26.2 DC Characteristics Table 26.2 DC Characteristics (Conditions: VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Max Measurement Unit Conditions VCC × 0.9 — VCC+ 0.3 V EXTAL VCC× 0.9 — VCC+ 0.3 V A/D port VCC× 0.7 — AVCC+ 0.3 V Other input pins VCC× 0.7 — VCC+ 0.3 V RES, NMI, VIL MD3–0, PA2, PA5, PA6–PA9, PA0–PE15, FWP –0.3 — VCC× 0.1 V –0.3 VCC× 0.07 — VCC× 0.2 V — — V — — A/D port — — 1.
Table 26.2 DC Characteristics (Conditions: VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) (cont) Item Pin Symbol Min Output high-level voltage All output pins VOH Typ Max Measurement Unit Conditions VCC– 0.5 — — V I OH = –200 µA VCC– 1.0 — — V I OH = –1mA VOL — — 0.4 V I OL = 1.6mA Cin — — 80* 2 pF Vin= 0V NMI — — 50 pF f = 1 MHz All other input pins — — 20 pF Ta = 25°C — 80 130 mA f = 16.
Table 26.3 Permitted Output Current Values (Conditions: VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Typ Max Unit Output low-level permissible current (per pin) I OL — — 2.0 mA Output low-level permissible current (total) ∑ IOL — — 80 mA Output high-level permissible current (per pin) –I OH — — 2.
tcyc tCL tCH CK 1/2VCC 1/2VCC tCF tCR Figure 26.1 System Clock Timing tEXcyc tEXH EXTAL 1/2VCC VIH tEXL VIH VIL VIL tEXF VIH 1/2VCC tEXR Figure 26.2 EXTAL Clock Input Timing CK VCC VCC min tOSC2 tOSC1 RES Figure 26.
26.3.2 Control Signal Timing Table 26.5 Control Signal Timing (Conditions: VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure RES rise/fall t RESr, t RESf — 200 ns 26.4 RES pulse width t RESW 20 — t cyc MRES pulse width t MRESW 20 — t cyc NMI rise/fall t NMIr, t NMIf — 200 ns 26.5 t RESS 100 — ns 26.4 t MRESS 100 — ns 26.
CK tRESf tRESr tRESS tRESS VIH RES VIH VIL VIL tRESW tMRESS tMRESS VIH MRES VIL VIL tMRESW Figure 26.4 Reset Input Timing CK tNMIH tNMIr,tNMIf tNMIS VIH NMI VIL tIRQEH IRQ edge tIRQES VIH VIL tIRQLS IRQ level Figure 26.
CK tIRQOD tIRQOD IRQOUT Figure 26.6 Interrupt Signal Output Timing CK tBRQS tBRQS BREQ (Input) tBACKD1 BACK (Output) RD, RDWR, RAS, CASxx, CSn, WRxx tBZD tBZD A21–A0, D31–D0 Note: During the bus-release period of a self-refresh, RAS, CASx, and RDWR are output. Figure 26.
26.3.3 Bus Timing Table 26.6 Bus Timing (Conditions: VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure Address delay time tAD 3*4 35 ns 26.8, 9, 11–16, 19 CS delay time 1 tCSD1 3*4 3*4 35 ns 26.
Table 26.7 Bus Timing (Conditions: VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure Write address setup time t AS 0 — ns 26.8, 9 Write address hold time t WR 5 — ns 26.8, 9, 19 Write data hold time t WRH 0 — ns 27 ns 27 ns Read/write strobe delay time 1 t RWD1 3* 2 Read/write strobe delay time 2 t RWD2 3* 2 High-speed page mode CAS t CP t cyc –35 — ns 26.
T1 T2 CK tAD A21–A0 tCSD1 tCSD2 CSn tRSD1 tOE tRSD2 RD (During read) tRDS tACC tRDH D31–D0 (During read) tWSD1 tWSD2 tWR WRxx (During write) tWRH tAS tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CSn, and RD. Figure 26.
T1 Tw T2 CK tAD A21–A0 tCSD1 tCSD2 CSn tRSD1 tRSD2 tOE RD (During read) tACC tRDH tRDS D31–D0 (During read) tWSD1 tWSD2 tWR WRxx (During write) tAS tWRH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CSn, and RD. Figure 26.
T1 Tw Tw Two T2 CK A21–A0 CSn RD (During read) D31–D0 (During read) WRxx (During write) D31–D0 (During write) tWTS tWTH tWTS tWTH WAIT DACKn Figure 26.
Tp Tr Tc1 Tc2 CK tAD tAD Column address Row address A21–A0 tRASD1 tASR tRAH tRASD2 RAS tRP tCASD1 tCASD2 CASxx (During read) RDWR tCAC (During read) tRDS tAA tRDH tRAC D31– D0 (During read) tCASD1 CASxx (During write) tCASD2 tRWD1 tRWD2 RDWR (During write) tDS tDH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn tRSD1 tRSD2 RD (During read) tWSD1 tWSD2 WRxx (During write) Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. Figure 26.
Tp Tr CK Tc1 Column address Row address tRASD1 tASR Tc2 tAD tAD A21–A0 RAS Tcw1 tRAH tRASD2 tRP tCASD1 tCASD2 CASxx (During read) RDWR (During read) tCAC tRDS tAA tRDH tRAC D31–D0 (During read) tCASD2 tCASD1 CASxx (During write) tRWD1 RDWR (During write) tRWD2 tDS tDH tWDD tWDH D31–D0 (During write) tDACKD1 tDACKD1 DACKn tRSD1 tRSD2 RD (During read) WRxx (During write) tWSD1 tWSD2 Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and CAS. Figure 26.
Tp Tpw Tr CK Trw Tc1 tAD Tcw1 Tc2 tAD Row address A21–A0 tRASD1 Column address tRASD2 tRAH tASR RAS Tcw2 tRP tCASD2 tCASD1 CASxx (During read) RDWR (During read) tCAC tRDS tAA tRDH tRAC D31–D0 (During read) tCASD1 CASxx (During write) tCASD2 tRWD1 tRWD2 RDWR (During write) tDS tWDD D31–D0 (During write) tDH tWDH tDACKD1 tDACKD1 DACKn tRSD1 RD (During read) tRSD2 tWSD1 tWSD2 WRxx (During write) Note: tRDH is specified from fastest negate timing of A21–A0, RAS, and
Tp Tr Tc1 Tcw1 Tcw2 Tcwo Tc2 CK tAD Row address A21–A0 tASR RAS tAD tRASD1 Column address tRAH tRASD2 tRP tCASD2 tCASD1 CASxx (During read) RDWR (During read) tCAC tAA tRAC D31–D0 (During read) tRDS tCASD2 tCASD1 CASxx (During write) tRWD1 RDWR (During write) tRDH tRWD2 tDS tDH tWDD tWDH D31–D0 (During write) tWTS tWTH tWTS tWTH WAIT tDACKD1 tDACKD1 DACKn tRSD1 RD (During read) tWSD1 WRxx (During write) tRSD2 tWSD2 Note: tRDH is specified from fastest negate timi
Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD tAD Column address Row address A21–A0 tRASD1 tASR RAS Column address tRAH tRASD2 tRP tCASD1 tCASD2 CASxx (During read) tCASD1 tCASD2 tCP RDWR (During read) tCAC tAA tRDS tCASD1 CASxx (During write) tRDH tRDH tRAC D31–D0 (During read) tCAC tAA tRDS tCASD2 tCASD1 tCASD2 tCP tRWD1 tRWD2 tRWD1 tRWD2 RDWR (During write) tDS tDH tDS tWDD D31–D0 (During write) tWDH tDACKD1 tDH tWDD tWDH tDACKD1 tDACKD1 DACKn tRSD2 tRSD1 RD (During
TRp TRr1 TRr2 TRc TRcc CK tRASD1 tRASD2 RAS tCSR tCASD1 tCASD2 CASxx RDWR Figure 26.18 Self Refresh Ta1 CK Ta2 Ta3 Ta4 T1 TW TWo T2 tAD A21–A0 tCSD1 tCSD2 CS3 tAHD1 tAHD2 AH tRSD1 RD (During read) tMAD D15–D0 (During read) tRSD2 tMAH tRDS tRDH Address tWSD1 tWSD2 WRxx (During write) tWR tMAD D15–D0 (During write) tMAH tWDD tWDH Address tWTS tWTH tWTS tWTH tWRH WAIT tDACKD1 tDACKD1 DACKn Note: tRDH is specified from fastest negate timing of A21–A0, CS3, and RD.
26.3.4 Direct Memory Access Controller Timing Table 26.8 Direct Memory Access Controller Timing (Conditions: VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure DREQ0, DREQ1 setup time t DRQS 35 — ns 26.20 DREQ0, DREQ1 hold time t DRQH 35 — ns DREQ0, DREQ1 pulse width t DRQW 1.5 — t cyc 26.21 DRAK output delay time t DRAKD — 35 ns 26.
CK DREQ0 DREQ1 Edge tDRQW Figure 26.21 DREQ0 and DREQ1 Input Timing (2) CK tDRAKD tDRAKD DRAKn Figure 26.
26.3.5 Multifunction Timer Pulse Unit Timing Table 26.9 Multifunction Timer Pulse Unit Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0 * to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure Output compare output delay time t TOCD — 100 ns 26.23 Input capture input setup time t TICS 100 — ns Timer input setup time t TCKS 100 — ns Timer clock pulse width (single edge specification) t TCKWH/L 1.
26.3.6 I/O Port Timing Table 26.10 I/O Port Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure Port output data delay time t PWD — 100 ns 26.25 Port input hold time t PRH 100 — ns Port input setup time t PRS 100 — ns Note: * SH7042/43 ZTAT (excluding A mask) are 3.2V. T1 T2 CK tPRS tPRH Port (Read) tPWD Port (Write) Figure 26.
26.3.7 Watchdog Timer Timing Table 26.11 Watchdog Timer Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min WDTOVF delay time t WOVD — Max Unit Figure 100 ns 26.26 Note: * SH7042/43 ZTAT (excluding A mask) are 3.2V. CK tWOVD tWOVD WDTOVF Figure 26.
26.3.8 Serial Communication Interface Timing Table 26.12 Serial Communication Interface Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0 * to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min Max Unit Figure Input clock cycle t scyc 4 — t cyc 26.27 Input clock cycle (clock sync) t scyc 6 — t cyc Input clock pulse width t sckw 0.5 0.6 t scyc Input clock rise time t sckr — 1.5 t cyc Input clock fall time t sckf — 1.
26.3.9 High-speed A/D Converter Timing (excluding A mask) Table 26.13 High-speed A/D Converter Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min External trigger input pulse width t TRGW External trigger input start delay time A/D conversion start delay time CKS = 0 Typ Max Unit Figure 2 — — t cyc 26.29 t TRGS 50 — — ns tD 1.5 1.5 1.5 t cyc 1.5 1.5 1.
φ Address Write signal ADST Sampling timing ADF tD tSPL tCP tCONV tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time tCP : Operation time Figure 26.
26.3.10 Mid-speed Converter Timing (A mask) Table 26.14 Mid-speed A/D Converter Timing (Conditions:VCC = 3.0* to 3.6V, AVCC = 3.0* to 3.6V, AVCC = VCC ± 10%, AVref = 3.0* to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) Item Symbol Min External trigger input pulse width t TRGW External trigger input start delay time A/D conversion start delay time CKS = 0 Typ Max Unit Figure 2 — — t cyc 26.
(1) CK (2) Address Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1) (2) tD t SPL t CONV : ADCSR write cycle : ADCSR address : A/D conversion start delay time : Input sampling time : A/D conversion time Figure 26.
26.3.11 Measurement Conditions for AC Characteristic • Input reference levels: High level: 2.2 V Low level: 0.8 V • Output reference levels: High level: 2.0 V Low level: 0.
26.4 A/D Converter Characteristics Table 26.15 A/D Converter Characteristics (excluding A mask) (Conditions:VCC = 3.0*1 to 3.6V, AVCC = 3.0*1 to 3.6V, AVCC = VCC ± 10%, AVref = 3.0*1 to AVCC , VSS = AVSS = 0V, T a = –20 to +75°C) 16.
812
Appendix A On-Chip Supporting Module Registers A.1 Addresses Table A.1 On-Chip I/O Register Addresses Bit Names Address Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 On-Chip I/O Register Addresses (cont) Bit Names Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Table A.1 Address On-Chip I/O Register Addresses (cont) Register Abbr.
Appendix B Block Diagrams PAR Internal data bus RES R PAn/ RXDm Q PAnDR D PFC C PAW Q PAnMD Q PAnIOR SBYCR Standby Q HIZ SCI RXDm n = 0, 3 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES PAn/ SCKm/ DREQm/ IRQm Q PAnDR D C PAW SCKmOUT PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ INTC IRQm DMAC DREQm SCI SCKmIN n = 2, 5 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PAnDR D C PAW PA6/ TCLKA/ CS2, PA7/ TCLKB/ CS3 CS2, CS3 PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ MTU TCLKA, TCLKB n = 6, 7 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
On-chip flash memory WE Writer mode Internal data bus PA7/TCLKB/CS3 PAR RES Q PA7DR D C PAW CS3 PFC Q PA7MD0 Q PA7MD1 Q PA7IOR SBYCR Standby Q HIZ MTU TCLKB PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PAnDR D C PAW PA8/ TCLKC/ IRQ2, PA9/ TCLKD/ IRQ3 PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ MTU TCLKC, TLCKD INTC IRQ2, IRQ3 n = 8, 9 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
On-chip flash memory OE, CE Writer mode Internal data bus PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PAR RES Q PAnDR D C PFC PAW Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ MTU TCLKC,D INTC IRQ2,IRQ3 n=8, 9 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PAnDR D C PAn/ TXDm TXDm PAW PFC Q PAnMD Q PAnIOR Standby STBCR Q HIZ n = 1, 4 m = 0, 1 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PA15DR D C PA15/CK CK PAW Single mode MCU mode 2 MCU mode 1 MCU mode 0 PFC Q PA15MD Q PA15IOR Standby STBCR Q HIZ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PA18DR D C PA18/ DRAK0/ BREQ PAW DRAK0 PFC Q PA18MD0 Q PA18IMD1 Q PA18IOR SBYCR Standby Q HIZ BSC BREQ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PA19DR D C PA19/ DRAK1/ BACK PAW Bus right release DRAK1 BACK PFC Q PA19MD0 Q PA19MD1 Q PA19IOR SBYCR Standby Q HIZ PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PAnDR D C PAn/ XXX CS0, CS1,WRL, WRH,RD Single mode PAW MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release Q PAnMD Q PAnIOR Standby SBYCR Q HIZ n = 10-14 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R Q PAnDR D C PAn/ XXXX AH, CASHL, CASHH,WRHL, WRHH Single mode PAW PFC Q PAnMD Bus right release Q PAnIOR Standby SBYCR Q HIZ n = 16,20-23 PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
PAR Internal data bus RES R PA17/ WAIT Q PAnDR D C PAW Single mode PFC Q PA17MD Bus right release Q PA17IOR Standby SBYCR Q HIZ WAIT request PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.
On-chip* EPROM A16 PBR Internal data bus PROM mode PB0/ A16 RES R Q PB0DR D C A16 PBW Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release Q PB0MD Q PB0IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Note: * Not available with the mask versions. Figure B.
On-chip flash memory A16 Internal data bus PBR RES PB0/A16 Writer mode Q PB0DR D C A16 PBW Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release PFC Q PB0MD0 Q PB0IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
PBR Internal data bus RES R Q PB1DR D C PB1/ A17 A17 PBW Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release Q PB1MD Q PB1IOR Standby SBYCR Q HIZ PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
PBR Internal data bus RES PB6/ IRQ4/ A18/ BACK Q PB6DR D C PBW A18 BACK PFC Q PB6MD0 Q PB6MD1 Q PB6IOR SBYCR Standby Bus right release PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
On-chip* EPROM OE, PGM PBR Internal data bus PROM mode PBn/ IRQm/ POEm/ CASx RES Q PBnDR D C PBW CASL, CASH PFC Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Bus right release Q HIZ POE POEm INTC IRQm n = 3, 4 m = 1, 2 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Note: * Not available with the ZTAT version. Figure B.
On-chip flash memory* A17 Internal data bus PBR RES PB4/IRQ2/POE2/CASH, PB3/IRQ1/POE1/CASL Writer mode Q PBnDR D C PBW CASL,CASH PFC Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right release POE POEm INTC IRQm Note: * Only when n = 4. n=3, 4 m=1, 2 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
PBR Internal data bus RES PBn/ IRQm/ XXX/ YYY Q PBnDR D C PBW A19–A21 PFC Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Bus right release Q HIZ BSC/AD BREQ, WAIT, ADTRG INTC IRQm n = 7-9 m = 5-7 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
PBR Internal data bus RES PBn/ IRQm/ XXX/ YYY Q PBnDR D C PBW RAS, RDWR PFC Q PBnMD0 Q PBnMD1 Q PBnIOR SBYCR Standby Q HIZ Bus right release POE POE0, POE3 INTC IRQm n = 2, 5 m = 0, 3 PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.
On-chip* EPROM An PCR Internal data bus PROM mode PCn/ An RES R Q PCnDR D C An PCW Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release Q PBnMD Q PBnIOR Standby SBYCR Q HIZ n = 0–15 PCR: Port C read signal PCW: Port C write signal RES: Reset signal Note: * Not available with the mask versions. Figure B.
On-chip flash memory An Internal data bus PCR RES PCn/An Writer mode Q PCnDR D C An PCW Single mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release PFC Q PCnMD Q PCnIOR Standby SBYCR Q HIZ n=0–15 PCR: Port C read signal PCW: Port C write signal RES: Reset signal Figure B.
On-chip* EPROM Dn PDR Internal data bus RES PROM mode R Q PDnDR D C PDn/ Dn Dn Dout PDW Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release SLEEP Q PDnMD Q PDnIOR Standby Din SBYCR Q HIZ n = 0–7 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Note: * Not available with the mask version. Figure B.
On-chip flash memory Dn Internal data bus PDR RES Writer mode PDn/Dn Q PDnDR D C Dn Dout PDW Single mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Bus right release Sleep Q PDnMD0 Q PDnIOR Standby Din SBYCR Q HIZ n=0–15 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data bus output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn/ IRQm Dn Dout PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release PFC SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby Din SBYCR Q HIZ INTC IRQm n = 16–23 m = 0–7 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn/ DREQm Dn Dout PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release PFC SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby Din SBYCR Q HIZ DMAC DREQm n = 24,25 m = 0,1 PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn/ DACKm Dn Dout DACKm Single mode PDW MCU mode 1 MCU mode 0 MCU mode 2 Bus right release PFC SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby Din n = 26,27 m = 0,1 PDR: Port D read signal PDW: Port D write signal SBYCR Q HIZ RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn/ CSm Dn Dout CSm PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP PFC QPDnMD0 QPDnMD1 QPDnIOR Standby Din n = 28–29 m = 2–3 PDR: Port D read signal PDW: Port D write signal Q HIZ RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn/ IRQOUT Dn Dout IRQOUT PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release PFC SLEEP QPDnMD0 QPDnMD1 QPDnIOR Standby Din n = 30 PDR: Port D read signal PDW: Port D write signal SBYCR Q HIZ RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PD31DR D C PD31/ D31/ ADTRG Dn Dout PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release PFC SLEEP QPD31MD0 QPD31MD1 QPD31IOR Standby Din SBYCR Q HIZ A/D ADTRG PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PDR Internal data bus RES R Q PDnDR D C PDn/ Dn Dn Dout PDW Single mode MCU mode 1 MCU mode 0 MCU mode 2 Bus right release SLEEP PFC QPDnMD QPDnIOR Standby Din n = 8–15 PDR: Port D read signal PDW: Port D write signal SBYCR Q HIZ RES: Reset signal Dout: Data output timing signal Din: Data bus input timing signal Figure B.
PER Internal data bus RES Q PE13DR D C PE13/ TIOC4B/ MRES PEW TIOC4B PFC QPE13MD0 QPE13MD1 QPE13IOR Standby SBYCR Q HIZ MTU TIOC4B SYSC MRES PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.
PER Internal data bus RES Q PE14DR D C PE14/ TIOC4C/ DACK0/ AH PEW TIOC4C DRAK0 AH PFC QPE14MD0 QPE14MD1 QPE14IOR SBYCR Standby Q HIZ MTU TIOC4C PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.
PER Internal data bus RES Q PE15DR D C PE15/ TIOC4D/ DACK1/ IRQOUT PEW TIOC4D DRAK1 IRQOUT PFC QPE15MD0 QPE15MD1 QPE15IOR SBYCR Standby Q HIZ MTU TIOC4D PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.
PER Internal data bus RES Q PEnDR C PEn/ TIOCxx D TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A, TIOC3B, TIOC3C, TIOC3D, TIOC4A PFC PEW QPEnMD QPEnIOR SBYCR Standby Q HIZ MTU n = 4-12 PER: Port E read signal PEW: Port E write signal RES: Reset signal TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A, TIOC3B, TIOC3C, TIOC3D, TIOC4A Figure B.
PER Internal data bus RES Q PEnDR C PEn/ TIOCxx/ DRACm D PEW TIOC0B TIOC0D DRAKm PFC QPEnMD0 QPEnMD1 QPEnIOR SBYCR Standby Q HIZ MTU TIOC0B TIOC0D n = 1, 3 m = 0, 1 PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.
PER Internal data bus RES Q PEnDR D C PEn/ TIOCxx/ DREQm PEW TIOC0A TIOC0C PFC QPEnMD0 QPEnMD1 QPEnIOR Standby SBYCR Q HIZ MTU TIOC0A TIOC0C DMA DREQm n = 0, 2 m = 0, 1 PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.
PFR Internal data bus PFn/ ANn Standby SBYCR Q HIZ AD ANn n = 0–7 PFR: Port F read signal Figure B.
Appendix C Pin States Table C.
Table C.
Table C.
Table C.
Table C.
Table C.
Table C.
Table C.
Table C.
Table C.
Appendix D Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM of the mask-ROM version and F– ZTAT version differ as follows.
Appendix E Product Code Lineup Table E.1 SH7040, SH7041, SH7042, SH7043, SH7044, and SH7045 Product Lineup Product Mask Type Version Product Code Mark Code Package Order Model No.
Table E.1 SH7040, SH7041, SH7042, SH7043, SH7044, and SH7045 Product Lineup (cont) Product Mask Type Version Product Code Mark Code Package Order Model No.
Appendix F Package Dimensions Package dimensions of the SH7040, SH7042, SH7044 (FP-112) are shown in figures F.1 and F.2. Package dimensions of the SH7040, SH7042 (TFP-120) are shown in figure F.3. Package dimensions of the SH7041, SH7043, SH7045 (FP-144) are shown in figures F.4 and F.5. Unit: mm 23.2 ± 0.3 20 84 57 56 112 29 0.65 23.2 ± 0.3 85 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.23 2.70 0.13 M 3.05 Max 28 1.6 0˚ – 8˚ 0.
This package (FP-112B) uses copper leads. Unit: mm 23.2 ± 0.2 20 84 57 56 112 29 0.65 23.2 ± 0.2 85 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.23 2.70 0.13 M 3.05 Max 28 1.6 0˚ – 8˚ 0.10 +0.15 –0.10 1 *0.32 ± 0.08 0.30 ± 0.06 0.8 ± 0.2 Package Code JEDEC JEITA Mass (reference value) FP-112B — Conforms 2.4 g Figure F.
Unit: mm 16.0 ± 0.2 14 90 61 60 120 31 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 0.07 M 1.2 1.00 30 0.10 ± 0.10 1 *0.17 ± 0.05 0.15 ± 0.04 1.20 Max 0.4 16.0 ± 0.2 91 1.0 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) Figure F.3 Package Dimensions (TFP-120) 880 TFP-120 — Conforms 0.
22.0 ± 0.2 20 108 Unit: mm 73 72 144 37 0.10 *Dimension including the plating thickness Base material dimension * 0.17 ± 0.05 0.15 ± 0.04 2.70 36 0.10 M 0.10 +0.15 –0.10 1 *0.22 ± 0.05 0.20 ± 0.04 3.05 Max 0.5 22.0 ± 0.2 109 1.25 1.0 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) FP-144J — Conforms 2.4 g Figure F.
This package (FP-144G) uses copper leads. 22.0 ± 0.2 20 108 Unit: mm 73 72 144 37 0.10 *Dimension including the plating thickness Base material dimension * 0.17 ± 0.05 0.15 ± 0.04 2.70 36 0.10 M 0.10 +0.15 –0.10 1 *0.22 ± 0.05 0.20 ± 0.04 3.05 Max 0.5 22.0 ± 0.2 109 1.25 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) Figure F.5 Package Dimensions (FP-144G) 882 1.0 FP-144G — Conforms 2.
SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual Publication Date: 1st Edition, February, 1997 Rev.6.00, May 26, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 1997, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Colophon 0.
SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0044-0600O
